Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION FORMAT
The VEX prefix is required to be the last prefix and immediately precedes the opcode bytes. It must follow any
other prefixes. If VEX prefix is present a REX prefix is not supported.
The 3-byte VEX leaves room for future expansion with 3 reserved bits. REX and the 66h/F2h/F3h prefixes are
reclaimed for future use.
VEX prefix has a two-byte form and a three byte form. If an instruction syntax can be encoded using the two-byte
form, it can also be encoded using the three byte form of VEX. The latter increases the length of the instruction by
one byte. This may be helpful in some situations for code alignment.
The VEX prefix supports 256-bit versions of floating-point SSE, SSE2, SSE3, and SSE4 instructions. VEX-encoded
128-bit vector integer instructions are supported in AVX. 256-bit vector integer instructions are supported in AVX2
but not AVX. Table B-1 of Appendix B lists promoted, VEX-128 encoded vector integer instructions in AVX.
Table B-2 lists 128-bit and 256-bit, promoted VEX-encoded vector integer instructions. Note, certain new instruction
functionality can only be encoded with the VEX prefix (See Appendix B, Table B-3, Table B-4, Table B-5).
The VEX prefix will #UD on any instruction containing MMX register sources or destinations.
The following subsections describe the various fields in two or three-byte VEX prefix:
4.1.4.1 VEX Byte 0, bits[7:0]
VEX Byte 0, bits [7:0] must contain the value 11000101b (C5h) or 11000100b (C4h). The 3-byte VEX uses the C4h
first byte, while the 2-byte VEX uses the C5h first byte.
4.1.4.2 VEX Byte 1, bit [7] - ‘R’
VEX Byte 1, bit [7] contains a bit analogous to a bit inverted REX.R. In protected and compatibility modes the bit
must be set to ‘1’ otherwise the instruction is LES or LDS. This bit is present in both 2- and 3-byte VEX prefixes.
The usage of WRXB bits for legacy instructions is explained in detail section 2.2.1.2 of Intel 64 and IA-32 Architectures
Software developer’s manual, Volume 2A. This bit is stored in bit inverted format.
4.1.4.3 3-byte VEX byte 1, bit[6] - ‘X’
Bit[6] of the 3-byte VEX byte 1 encodes a bit analogous to a bit inverted REX.X. It is an extension of the SIB Index
field in 64-bit modes. In 32-bit modes, this bit must be set to ‘1’ otherwise the instruction is LES or LDS. This bit is
available only in the 3-byte VEX prefix. This bit is stored in bit inverted format.
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