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Intel® Architecture Instruction Set Extensions Programming Reference

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A.5 ESCAPE OPCODE INSTRUCTIONS<br />

OPCODE MAP<br />

Opcode maps for coprocessor escape instruction opcodes (x87 floating-point instruction opcodes) are in Table A-7<br />

through Table A-22. These maps are grouped by the first byte of the opcode, from D8-DF. Each of these opcodes<br />

has a ModR/M byte. If the ModR/M byte is within the range of 00H-BFH, bits 3-5 of the ModR/M byte are used as<br />

an opcode extension, similar to the technique used for 1-and 2-byte opcodes (see A.4). If the ModR/M byte is<br />

outside the range of 00H through BFH, the entire ModR/M byte is used as an opcode extension.<br />

A.5.1 Opcode Look-up Examples for Escape <strong>Instruction</strong> Opcodes<br />

Examples are provided below.<br />

Example A-6. Opcode with ModR/M Byte in the 00H through BFH Range<br />

DD0504000000H can be interpreted as follows:<br />

• The instruction encoded with this opcode can be located in Section . Since the ModR/M byte (05H) is within the<br />

00H through BFH range, bits 3 through 5 (000) of this byte indicate the opcode for an FLD double-real<br />

instruction (see Table A-9).<br />

• The double-real value to be loaded is at 00000004H (the 32-bit displacement that follows and belongs to this<br />

opcode).<br />

Example A-7. Opcode with ModR/M Byte outside the 00H through BFH Range<br />

D8C1H can be interpreted as follows:<br />

• This example illustrates an opcode with a ModR/M byte outside the range of 00H through BFH. The instruction<br />

can be located in Section A.4.<br />

• In Table A-8, the ModR/M byte C1H indicates row C, column 1 (the FADD instruction using ST(0), ST(1) as<br />

operands).<br />

A.5.2 Escape Opcode <strong>Instruction</strong> Tables<br />

Tables are listed below.<br />

A.5.2.1 Escape Opcodes with D8 as First Byte<br />

Table A-7 and A-8 contain maps for the escape instruction opcodes that begin with D8H. Table A-7 shows the map if the ModR/M<br />

byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction.<br />

Table A-7. D8 Opcode Map When ModR/M Byte is Within 00H to BFH *<br />

nnn Field of ModR/M Byte (refer to Figure A.4)<br />

000B 001B 010B 011B 100B 101B 110B 111B<br />

FADD<br />

FMUL<br />

FCOM FCOMP FSUB<br />

FSUBR<br />

FDIV<br />

FDIVR<br />

single-real<br />

NOTES:<br />

single-real single-real single-real single-real single-real single-real single-real<br />

* All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.<br />

Ref. # 319433-014 A-21

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