Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

0 Table A-5. Three-byte Opcode Map: 08H — FFH (First Two Bytes are 0F 3AH) * pfx 8 9 A B C D E F 66 1 66 2 3 66 4 66 5 6 vroundps Vx,Wx,Ib vinsertf128 v Vqq,Hqq,Wqq,Ib vinserti128 v Vqq,Hqq,Wqq,Ib vroundpd Vx,Wx,Ib vextractf128 v Wdq,Vqq,Ib vextracti128 v Wdq,Vqq,Ib vroundss Vss,Wss,Ib vblendvps v Vx,Hx,Wx,Lx vroundsd Vsd,Wsd,Ib vblendvpd v Vx,Hx,Wx,Lx vblendps Vx,Hx,Wx,Ib vpblendvb v Vx,Hx,Wx,Lx vblendpd Vx,Hx,Wx,Ib vcvtps2phv Wx, Vx, Ib vpblendw Vx,Hx,Wx,Ib OPCODE MAP palignr Pq, Qq, Ib vpalignr Vx,Hx,Wx,Ib 7 8 9 A B C D E F 66 VAESKEYGEN Vdq, Wdq, Ib NOTES: * All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations. Ref. # 319433-014 A-17
OPCODE MAP A.4 OPCODE EXTENSIONS FOR ONE-BYTE AND TWO-BYTE OPCODES Some 1-byte and 2-byte opcodes use bits 3-5 of the ModR/M byte (the nnn field in Figure A-1) as an extension of the opcode. Opcodes that have opcode extensions are indicated in Table A-6 and organized by group number. Group numbers (from 1 to 16, second column) provide a table entry point. The encoding for the r/m field for each instruction can be established using the third column of the table. A.4.1 Opcode Look-up Examples Using Opcode <strong>Extensions</strong> An Example is provided below. Example A-4. Interpreting an ADD <strong>Instruction</strong> An ADD instruction with a 1-byte opcode of 80H is a Group 1 instruction: • Table A-6 indicates that the opcode extension field encoded in the ModR/M byte for this instruction is 000B. • The r/m field can be encoded to access a register (11B) or a memory address using a specified addressing mode (for example: mem = 00B, 01B, 10B). Example A-5. Looking Up 0F01C3H Look up opcode 0F01C3 for a VMRESUME instruction by using Table A-2, Table A-3 and Table A-6: • 0F tells us that this instruction is in the 2-byte opcode map. • 01 (row 0, column 1 in Table A-3) reveals that this opcode is in Group 7 of Table A-6. • C3 is the ModR/M byte. The first two bits of C3 are 11B. This tells us to look at the second of the Group 7 rows in Table A-6. • The Op/Reg bits [5,4,3] are 000B. This tells us to look in the 000 column for Group 7. • Finally, the R/M bits [2,1,0] are 011B. This identifies the opcode as the VMRESUME instruction. A.4.2 Opcode Extension Tables See Table A-6 below. mod nnn R/M Figure A-1. ModR/M Byte nnn Field (Bits 5, 4, and 3) A-18 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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Page 461 and 462: INSTRUCTION SUMMARY Table B-3. VEX-
Page 463 and 464: INSTRUCTION SUMMARY Opcode Instruct
Page 473 and 474: SSE extensions flag . . . . . . . .
Page 475 and 476: SSE extensions CPUID flag . . . . .
Page 477: I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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