Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM register are
zeroed.
VEX.256 encoded version: The first source and destination operands are YMM registers. The second source
operand is an YMM register or a 256-bit memory location.
Operation
BYTE_SIGN_256b(SRC1, SRC2)
if (SRC2[7..0] < 0 )
DEST[7...0] Neg(SRC1[7...0])
else if(SRC2[7..0] == 0 )
DEST[7...0] 0
else if(SRC2[7..0] > 0 )
DEST[7...0] SRC1[7...0]
Repeat operation for 2nd through 31th bytes
if (SRC2[255...248] < 0 )
DEST[255...248] Neg(SRC1[255...248])
else if(SRC2[255...248] == 0 )
DEST[255...248] 0
else if(SRC2[255...248] > 0 )
DEST[255...248] SRC1[255...248]
BYTE_SIGN(SRC1, SRC2)
if (SRC2[7..0] < 0 )
DEST[7...0] Neg(SRC1[7...0])
else if(SRC2[7..0] == 0 )
DEST[7...0] 0
else if(SRC2[7..0] > 0 )
DEST[7...0] SRC1[7...0]
Repeat operation for 2nd through 15th bytes
if (SRC2[127..120] < 0 )
DEST[127...120] Neg(SRC1[127...120])
else if(SRC2[127.. 120] == 0 )
DEST[127...120] 0
else if(SRC2[127.. 120] > 0 )
DEST[127...120] SRC1[127...120]
WORD_SIGN_256b(SRC1, SRC2)
if (SRC2[15..0] < 0 )
DEST[15...0] Neg(SRC1[15...0])
else if(SRC2[15..0] == 0 )
DEST[15...0] 0
else if(SRC2[15..0] > 0 )
DEST[15...0] SRC1[15...0]
Repeat operation for 2nd through 15th words
if (SRC2[255..240] < 0 )
DEST[255..240] Neg(SRC1[255..240])
else if(SRC2[255..240] == 0 )
DEST[255..240] 0
else if(SRC2[255..240] > 0 )
Ref. # 319433-014 5-129