Intel® Architecture Instruction Set Extensions Programming Reference

5.1.6 CPUID Support column in the Instruction Summary Table
INSTRUCTION SET REFERENCE
The fourth column holds abbreviated CPUID feature flags (e.g. appropriate bit in CPUID.1.ECX, CPUID.1.EDX,
CPUID.(EAX=7,ECX=0).EBX, CPUID.80000001H.ECX for
SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2/AVX/FP16/RDRAND/AVX2/BMI1/BMI2/LZCNT support) that indicate
processor support for the instruction. If the corresponding flag is ‘0’, the instruction will #UD.
5.2 SUMMARY OF TERMS
• “Legacy SSE”: Refers to SSE, SSE2, SSE3, SSSE3, SSE4, and any future instruction sets referencing XMM
registers and encoded without a VEX prefix.
• XGETBV, XSETBV, XSAVE, XRSTOR are defined in IA-32 Intel Architecture Software Developer’s Manual,
Volumes 3A and Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
• VEX: refers to a two-byte or three-byte prefix. AVX and FMA instructions are encoded using a VEX prefix.
• VEX.vvvv. The VEX bitfield specifying a source or destination register (in 1’s complement form).
• rm_field: shorthand for the ModR/M r/m field and any REX.B
• reg_field: shorthand for the ModR/M reg field and any REX.R
• VLMAX: the maximum vector register width pertaining to the instruction. This is not the vector-length
encoding in the instruction's prefix but is instead determined by the current value of XCR0. For existing
processors, VLMAX is 256 whenever XFEATURE_ENABLED_MASK.YMM[bit 2] is 1. Future processors may
defined new bits in XFEATURE_ENABLED_MASK whose setting may imply other values for VLMAX.
5.3 INSTRUCTION SET REFERENCE
VLMAX Definition
XCR0 Component VLMAX
XCR0.YMM 256
Ref. # 319433-014 5-5