Intel® Architecture Instruction Set Extensions Programming Reference

SYSTEM PROGRAMMING MODEL
• Verify the processor supports XSAVE/XRSTOR/XSETBV/XGETBV instructions and the
XFEATURE_ENABLED_MASK register by checking CPUID.1.ECX.XSAVE[bit 26]=1.
• Verify the processor supports YMM state (i.e. bit 2 of XFEATURE_ENABLED_MASK is valid) by checking
CPUID.(EAX=0DH, ECX=0):EAX.YMM[2]. The OS should also verify CPUID.(EAX=0DH, ECX=0):EAX.SSE[bit
1]=1, because the lower 128-bits of an YMM register are aliased to an XMM register.
The OS must determine the buffer size requirement for the XSAVE area that will be used by XSAVE/XRSTOR
(see CPUID instruction in Section 2.9).
• Set CR4.OSXSAVE[bit 18]=1 to enable the use of XSETBV/XGETBV instructions to write/read the
XFEATURE_ENABLED_MASK register.
• Supply an appropriate mask via EDX:EAX to execute XSETBV to enable the processor state components that
the OS wishes to manage using XSAVE/XRSTOR instruction. To enable x87 FPU, SSE and YMM state
management using XSAVE/XRSTOR, the enable mask is EDX=0H, EAX=7H (The individual bits of
XFEATURE_ENABLED_MASK is listed in Table 3-1).
To enable YMM state, the OS must use EDX:EAX[2:1] = 11B when executing XSETBV. An attempt to execute
XSETBV with EDX:EAX[2:1] = 10B causes a #GP(0) exception.
Table 3-1. XFEATURE_ENABLED_MASK and Processor State Components
Bit Meaning
0 - x87
1 - SSE
2 - YMM
3.2.3 Enabling of SIMD Floating-Exception Support
AVX and FMA instruction may generate SIMD floating-point exceptions. An OS must enable SIMD floating-point
exception support by setting CR4.OSXMMEXCPT[bit 10]=1.
The effect of CR4 setting that affects AVX and FMA enabling is listed in Table 3-2
3.2.4 The Layout of XSAVE Area
If set, the processor supports x87 FPU state management via XSAVE/XRSTOR. This bit must be 1 if
CPUID.01H:ECX.XSAVE[26] = 1.
If set, the processor supports SSE state (XMM and MXCSR) management via XSAVE/XRSTOR. This bit
must be set to ‘1’ to enable AVX.
If set, the processor supports YMM state (upper 128 bits of YMM registers) management via XSAVE. This
bit must be set to ‘1’ to enable AVX and FMA.
Table 3-2. CR4 bits for AVX New Instructions technology support
Bit Meaning
CR4.OSXSAVE[bit 18] If set, the OS supports use of XSETBV/XGETBV instruction to access the XFEATURE_ENABLED_MASK
register, XSAVE/XRSTOR to manage processor extended state. Must be set to ‘1’ to enable AVX and
FMA.
CR4.OSXMMEXCPT[bit 10] Must be set to 1 to enable SIMD floating-point exceptions. This applies to AVX, FMA operating on YMM
states, and legacy 128-bit SIMD floating-point instructions operating on XMM states.
CR4.OSFXSR[bit 9] Ignored by AVX and FMA instructions operating on YMM states.
Must be set to 1 to enable SIMD instructions operating on XMM state.
The OS must determine the buffer size requirement by querying CPUID with EAX=0DH, ECX=0. If the OS wishes to
enable all processor extended state components in the XFEATURE_ENABLED_MASK, it can allocate the buffer size
according to CPUID.(EAX=0DH, ECX=0):ECX.
After the memory buffer for XSAVE is allocated, the entire buffer must to cleared to zero prior to use by XSAVE.
For processors that support SSE and YMM states, the XSAVE area layout is listed in Table 3-3. The register fields of
the first 512 byte of the XSAVE area are identical to those of the FXSAVE/FXRSTOR area.
3-2 Ref. # 319433-014