Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
Instruction Operand Encoding
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA
Description
Unpacks and interleaves the low-order data elements (bytes, words, doublewords, and quadwords) of the first
source operand and second source operand into the destination operand. (Figure 5-6 shows the unpack operation
for bytes in 64-bit operands.). The high-order data elements are ignored.
SRC Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0 DEST
Y3 X3 Y2 X2 Y1 X1 Y0
Figure 5-6. 128-bit PUNPCKLBW Instruction Operation using 64-bit Operands
When the source data comes from a 128-bit memory operand an implementation may fetch only the appropriate
64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.
The PUNPCKLBW instruction interleaves the low-order bytes of the source and destination operands, the
PUNPCKLWD instruction interleaves the low-order words of the source and destination operands, the PUNPCKLDQ
instruction interleaves the low order doubleword (or doublewords) of the source and destination operands, and the
PUNPCKLQDQ instruction interleaves the low-order quadwords of the source and destination operands.
Legacy SSE instructions: In 64-bit mode using a REX prefix in the form of REX.R permits this instruction to access
additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (255:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (127:128) of the corresponding YMM register are
zeroed.
VEX.256 encoded version: The second source operand is an YMM register or a 256-bit memory location. The first
source operand and destination operands are YMM registers.
SRC
255
Y7 Y6 Y5
Y4
DEST
Y3 Y2 Y1 Y0 X7 X6 X5 X4
DEST
31
255
0
Y5 X5 Y4 X4 Y1 X1 Y0
Figure 5-7. 256-bit VPUNPCKLDQ Instruction Operation
5-166 Ref. # 319433-014
X0
255 31
X3 X2 X1
X0
0
X0
0