Intel® Architecture Instruction Set Extensions Programming Reference

INTEL® ADVANCED VECTOR EXTENSIONS
1.5.1 256-bit Floating-Point Arithmetic Processing Enhancements
Intel AVX provides 35 256-bit floating-point arithmetic instructions. The arithmetic operations cover add, subtract,
multiply, divide, square-root, compare, max, min, round, etc., on single-precision and double-precision floatingpoint
data.
The enhancement in AVX on floating-point compare operation provides 32 conditional predicates to improve
programming flexibility in evaluating conditional expressions.
FMA provides 36 256-bit floating-point instructions to perform computation on 256-bit vectors. The arithmetic
operations cover fused multiply-add, fused multiply-subtract, fused multiply add/subtract interleave, signedreversed
multiply on fused multiply-add and multiply-subtract.
1.5.2 256-bit Non-Arithmetic Instruction Enhancements
Intel AVX provides new primitives for handling data movement within 256-bit floating-point vectors and promotes
many 128-bit floating data processing instructions to handle 256-bit floating-point vectors.
AVX includes 39 256-bit data processing instructions that are promoted from previous generations of SIMD instruction
extensions, ranging from logical, blend, convert, test, unpacking, shuffling, load and stores.
AVX introduces 18 new data processing instructions that operate on 256-bit vectors. These new primitives cover
the following operations:
• Non-unit-stride fetching of SIMD data. AVX provides several flexible SIMD floating-point data fetching
primitives:
— broadcast of single or multiple data elements into a 256-bit destination,
— masked move primitives to load or store SIMD data elements conditionally,
• Intra-register manipulation of SIMD data elements. AVX provides several flexible SIMD floating-point data
manipulation primitives:
— insert/extract multiple SIMD floating-point data elements to/from 256-bit SIMD registers
— permute primitives to facilitate efficient manipulation of floating-point data elements in 256-bit SIMD
registers
• Branch handling. AVX provides several primitives to enable handling of branches in SIMD programming:
— new variable blend instructions supports four-operand syntax with non-destructive source syntax. This is
more flexible than the equivalent SSE4 instruction syntax which uses the XMM0 register as the implied
mask for blend selection.
— Packed TEST instructions for floating-point data.
1.5.3 Arithmetic Primitives for 128-bit Vector and Scalar processing
Intel AVX provides 131 128-bit numeric processing instructions that employ VEX-prefix encoding. These VEXencoded
instructions generally provide the same functionality over instructions operating on XMM register that are
encoded using SIMD prefixes. The 128-bit numeric processing instructions in AVX cover floating-point and integer
data processing across 128-bit vector and scalar processing.
The enhancement in AVX on 128-bit floating-point compare operation provides 32 conditional predicates to
improve programming flexibility in evaluating conditional expressions. This contrasts with floating-point SIMD
compare instructions in SSE and SSE2 supporting only 8 conditional predicates.
FMA provides 60 128-bit floating-point instructions to process 128-bit vector and scalar data. The arithmetic operations
cover fused multiply-add, fused multiply-subtract, signed-reversed multiply on fused multiply-add and
multiply-subtract.
1.5.4 Non-Arithmetic Primitives for 128-bit Vector and Scalar Processing
Intel AVX provides 126 data processing instructions that employ VEX-prefix encoding. These VEX-encoded instructions
generally provide the same functionality over instructions operating on XMM register that are encoded using
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