Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
(V)ADDSD ADD Scalar Double — Precision Floating-Point Values (THIS IS AN EXAMPLE)
Opcode/
Instruction
Op/
En
64/32bit
Mode
CPUID
Feature
Flag
Description
F2 0F 58 /r A V/V SSE2 Add the low double-precision floating-point value from
xmm2/mem to xmm1 and store the result in xmm1.
ADDSD xmm1, xmm2/m64
VEX.NDS.128.F2.0F.WIG 58 /r B V/V AVX Add the low double-precision floating-point value from
xmm3/mem to xmm2 and store the result in xmm1.
VADDSD xmm1, xmm2,
xmm3/m64
Instruction Operand Encoding
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
5.1.2 Opcode Column in the Instruction Summary Table
For notation and conventions applicable to instructions that do not use VEX prefix, consult Section 3.1 of the Intel
64 and IA-32 Architectures Software Developer’s Manual Volume 2A.
In the Instruction Summary Table, the Opcode column presents each instruction encoded using the VEX prefix in
following form (including the modR/M byte if applicable, the immediate byte if applicable):
VEX.[NDS,NDD,DDS].[128,256,LZ,LIG].[66,F2,F3].0F/0F3A/0F38.[W0,W1, WIG] opcode [/r]
[/ib,/is4]
• VEX: indicates the presence of the VEX prefix is required. The VEX prefix can be encoded using the three-byte
form (the first byte is C4H), or using the two-byte form (the first byte is C5H). The two-byte form of VEX only
applies to those instructions that do not require the following fields to be encoded: VEX.mmmmm, VEX.W,
VEX.X, VEX.B. Refer to Section 4.1.4 for more detail on the VEX prefix
The encoding of various sub-fields of the VEX prefix is described using the following notations:
— NDS, NDD, DDS: specifies that VEX.vvvv field is valid for the encoding of a register operand:
• VEX.NDS: VEX.vvvv encodes the first source register in an instruction syntax where the content of
source registers will be preserved.
• VEX.NDD: VEX.vvvv encodes the destination register that cannot be encoded by ModR/M:reg field.
• VEX.DDS: VEX.vvvv encodes the second source register in a three-operand instruction syntax where
the content of first source register will be overwritten by the result.
• If none of NDS, NDD, and DDS is present, VEX.vvvv must be 1111b (i.e. VEX.vvvv does not encode an
operand). The VEX.vvvv field can be encoded using either the 2-byte or 3-byte form of the VEX prefix.
— 128,256,LZ,LIG: VEX.L field can be 0 (denoted by VEX.128 or VEX.LZ) or 1 (denoted by VEX.256). The
VEX.L field can be encoded using either the 2-byte or 3-byte form of the VEX prefix. The presence of the
notation VEX.256 or VEX.128 in the opcode column should be interpreted as follows:
• If VEX.256 is present in the opcode column: The semantics of the instruction must be encoded with
VEX.L = 1. An attempt to encode this instruction with VEX.L= 0 can result in one of two situations: (a)
if VEX.128 version is defined, the processor will behave according to the defined VEX.128 behavior; (b)
an #UD occurs if there is no VEX.128 version defined.
• If VEX.128 is present in the opcode column but there is no VEX.256 version defined for the same opcode
byte: Two situations apply: (a) For VEX-encoded, 128-bit SIMD integer instructions, software must
encode the instruction with VEX.L = 0. The processor will treat the opcode byte encoded with VEX.L= 1
by causing an #UD exception; (b) For VEX-encoded, 128-bit packed floating-point instructions,
5-2 Ref. # 319433-014