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Intel® Architecture Instruction Set Extensions Programming Reference

Intel® Architecture Instruction Set Extensions Programming Reference

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INSTRUCTION SET REFERENCE - FMA<br />

VFMADD132SD/VFMADD213SD/VFMADD231SD — Fused Multiply-Add of Scalar Double-<br />

Precision Floating-Point Values<br />

Opcode/<br />

<strong>Instruction</strong><br />

VEX.DDS.LIG.128.66.0F38.W1<br />

99 /r<br />

VFMADD132SD xmm0, xmm1,<br />

xmm2/m64<br />

VEX.DDS.LIG.128.66.0F38.W1<br />

A9 /r<br />

VFMADD213SD xmm0, xmm1,<br />

xmm2/m64<br />

VEX.DDS.LIG.128.66.0F38.W1<br />

B9 /r<br />

VFMADD231SD xmm0, xmm1,<br />

xmm2/m64<br />

Description<br />

Op/<br />

En<br />

64/32<br />

-bit<br />

Mode<br />

CPUID<br />

Feature<br />

Flag<br />

Description<br />

A V/V FMA Multiply scalar double-precision floating-point value from xmm0 and<br />

xmm2/mem, add to xmm1 and put result in xmm0.<br />

A V/V FMA Multiply scalar double-precision floating-point value from xmm0 and<br />

xmm1, add to xmm2/mem and put result in xmm0.<br />

A V/V FMA Multiply scalar double-precision floating-point value from xmm1 and<br />

xmm2/mem, add to xmm0 and put result in xmm0.<br />

<strong>Instruction</strong> Operand Encoding<br />

Op/En Operand 1 Operand 2 Operand 3 Operand 4<br />

A ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA<br />

Performs a SIMD multiply-add computation on the low packed double-precision floating-point values using three<br />

source operands and writes the multiply-add result in the destination operand. The destination operand is also the<br />

first source operand. The second operand must be a SIMD register. The third source operand can be a SIMD<br />

register or a memory location.<br />

VFMADD132SD: Multiplies the low packed double-precision floating-point value from the first source operand to<br />

the low packed double-precision floating-point value in the third source operand, adds the infinite precision intermediate<br />

result to the low packed double-precision floating-point values in the second source operand, performs<br />

rounding and stores the resulting packed double-precision floating-point value to the destination operand (first<br />

source operand).<br />

VFMADD213SD: Multiplies the low packed double-precision floating-point value from the second source operand to<br />

the low packed double-precision floating-point value in the first source operand, adds the infinite precision intermediate<br />

result to the low packed double-precision floating-point value in the third source operand, performs rounding<br />

and stores the resulting packed double-precision floating-point value to the destination operand (first source<br />

operand).<br />

VFMADD231SD: Multiplies the low packed double-precision floating-point value from the second source to the low<br />

packed double-precision floating-point value in the third source operand, adds the infinite precision intermediate<br />

result to the low packed double-precision floating-point value in the first source operand, performs rounding and<br />

stores the resulting packed double-precision floating-point value to the destination operand (first source operand).<br />

VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in<br />

reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a<br />

XMM register or a 64-bit memory location and encoded in rm_field. The upper bits ([255:128]) of the YMM destination<br />

register are zeroed.<br />

Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the<br />

opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations<br />

involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction<br />

column. See also Section 2.3.1, “FMA <strong>Instruction</strong> Operand Order and Arithmetic Behavior”.<br />

6-8 Ref. # 319433-014

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