Intel® Architecture Instruction Set Extensions Programming Reference

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INSTRUCTION SET REFERENCE PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ — Compare Packed Integers for Greater Than Opcode/ <strong>Instruction</strong> Op/ En 64/32 -bit Mode CPUID Feature Flag Description 66 0F 64 /r A V/V SSE2 Compare packed signed byte integers in xmm1 and xmm2/m128 for greater than. PCMPGTB xmm1, xmm2/m128 66 0F 65 /r A V/V SSE2 Compare packed signed word integers in xmm1 and xmm2/m128 for greater than. PCMPGTW xmm1, xmm2/m128 66 0F 66 /r A V/V SSE2 Compare packed signed doubleword integers in xmm1 and xmm2/m128 for greater than. PCMPGTD xmm1, xmm2/m128 66 0F 38 37 /r A V/V SSE4_2 Compare packed qwords in xmm2/m128 and xmm1 for greater than. PCMPGTQ xmm1, xmm2/m128 VEX.NDS.128.66.0F.WIG 64 /r B V/V AVX Compare packed signed byte integers in xmm2 and xmm3/m128 for greater than. VPCMPGTB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG 65 /r B V/V AVX Compare packed signed word integers in xmm2 and xmm3/m128 for greater than. VPCMPGTW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG 66 /r B V/V AVX Compare packed signed doubleword integers in xmm2 and xmm3/m128 for greater than. VPCMPGTD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F38.WIG 37 /r B V/V AVX Compare packed signed qwords in xmm2 and xmm3/m128 for greater than. VPCMPGTQ xmm1, xmm2, xmm3/m128 VEX.NDS.256.66.0F.WIG 64 /r B V/V AVX2 Compare packed signed byte integers in ymm2 and ymm3/m256 for greater than. VPCMPGTB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG 65 /r B V/V AVX2 Compare packed signed word integers in ymm2 and ymm3/m256 for greater than. VPCMPGTW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG 66 /r B V/V AVX2 Compare packed signed doubleword integers in ymm2 and ymm3/m256 for greater than. VPCMPGTD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F38.WIG 37 /r B V/V AVX2 Compare packed signed qwords in ymm2 and ymm3/m256 for greater than. VPCMPGTQ ymm1, ymm2, ymm3/m256 <strong>Instruction</strong> Operand Encoding Op/En Operand 1 Operand 2 Operand 3 Operand 4 A ModRM:reg (r, w) ModRM:r/m (r) NA NA B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA Ref. # 319433-014 5-53
INSTRUCTION SET REFERENCE Description Performs a SIMD signed compare for the greater value of the packed byte, word, doubleword, or quadword integers in the first source operand and the second source operand. If a data element in the first source operand is greater than the corresponding date element in the second source operand the corresponding data element in the destination operand is set to all 1s, otherwise it is set to all 0s. The (V)PCMPGTB instruction compares the corresponding signed byte integers in the first and second source operands; the (V)PCMPGTW instruction compares the corresponding signed word integers in the first and second source operands; the (V)PCMPGTD instruction compares the corresponding signed doubleword integers in the first and second source operands, and the (V)PCMPGTQ instruction compares the corresponding signed qword integers in the first and second source operands. Legacy SSE instructions: In 64-bit mode using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15). The second source operand can be an XMM register or a 128-bit memory location. The first source operand and destination operand are XMM registers. 128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The first source operand and destination operand are XMM registers. Bits (255:128) of the corresponding YMM destination register remain unchanged. VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source operand and destination operand are XMM registers. Bits (255:128) of the corresponding YMM register are zeroed. VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. Operation COMPARE_BYTES_GREATER (SRC1, SRC2) IF SRC1[7:0] > SRC2[7:0] THEN DEST[7:0] FFH; ELSE DEST[7:0] 0; FI; (* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *) IF SRC1[127:120] > SRC2[127:120] THEN DEST[127:120] FFH; ELSE DEST[127:120] 0; FI; COMPARE_WORDS_GREATER (SRC1, SRC2) IF SRC1[15:0] > SRC2[15:0] THEN DEST[15:0] FFFFH; ELSE DEST[15:0] 0; FI; (* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *) IF SRC1[127:112] > SRC2[127:112] THEN DEST[127:112] FFFFH; ELSE DEST[127:112] 0; FI; COMPARE_DWORDS_GREATER (SRC1, SRC2) IF SRC1[31:0] > SRC2[31:0] THEN DEST[31:0] FFFFFFFFH; ELSE DEST[31:0] 0; FI; (* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *) IF SRC1[127:96] > SRC2[127:96] THEN DEST[127:96] FFFFFFFFH; ELSE DEST[127:96] 0; FI; COMPARE_QWORDS_GREATER (SRC1, SRC2) IF SRC1[63:0] > SRC2[63:0] THEN DEST[63:0] FFFFFFFFFFFFFFFFH; 5-54 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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Page 91 and 92: INSTRUCTION SET REFERENCE MPSADBW
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Page 105 and 106: INSTRUCTION SET REFERENCE PACKUSDW
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Page 111 and 112: INSTRUCTION SET REFERENCE PADDB/PAD
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Page 115 and 116: INSTRUCTION SET REFERENCE PADDSB/PA
Page 117 and 118: INSTRUCTION SET REFERENCE PADDUSB/P
Page 119 and 120: INSTRUCTION SET REFERENCE PALIGNR
Page 121 and 122: INSTRUCTION SET REFERENCE PAND —
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Page 125 and 126: INSTRUCTION SET REFERENCE PAVGB/PAV
Page 127 and 128: INSTRUCTION SET REFERENCE PBLENDVB
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Page 131 and 132: INSTRUCTION SET REFERENCE PBLENDW
Page 133 and 134: INSTRUCTION SET REFERENCE ELSE DEST
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Page 147 and 148: INSTRUCTION SET REFERENCE PHSUBW/PH
Page 153 and 154: INSTRUCTION SET REFERENCE PMADDUBSW
Page 155 and 156: INSTRUCTION SET REFERENCE VPMADDWD
Page 157 and 158: INSTRUCTION SET REFERENCE VEX.128 e
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Page 173 and 174: INSTRUCTION SET REFERENCE PMOVMSKB
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Page 177 and 178: INSTRUCTION SET REFERENCE VPMOVSXWQ
Page 179 and 180: INSTRUCTION SET REFERENCE PMOVZX
Page 181 and 182: INSTRUCTION SET REFERENCE Packed_Ze
Page 183 and 184: INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE DEST[15:0
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE DEST[175:
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE DEST[95:8
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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