Intel® Architecture Instruction Set Extensions Programming Reference

PHSUBSW — Packed Horizontal Subtract with Saturation
Opcode/
Instruction
Description
Op/
En
64/32
-bit
Mode
CPUID
Feature
Flag
Description
Instruction Operand Encoding
INSTRUCTION SET REFERENCE
66 0F 38 07 /r A V/V SSSE3 Subtract 16-bit signed integer horizontally, pack saturated integers
to xmm1.
PHSUBSW xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 07 /r B V/V AVX Subtract 16-bit signed integer horizontally, pack saturated integers
to xmm1.
VPHSUBSW xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.WIG 07 /r B V/V AVX2 Subtract 16-bit signed integer horizontally, pack saturated integers
to ymm1.
VPHSUBSW ymm1, ymm2,
ymm3/m256
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA
(V)PHSUBSW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the
most significant word from the least significant word of each pair in the second source and first source operands.
The signed, saturated 16-bit results are packed to the destination operand. The destination and first source
operand are XMM registers. The second operand can be an XMM register or a 128-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM register are
zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
Ref. # 319433-014 5-65