Intel® Architecture Instruction Set Extensions Programming Reference

More documents

Recommendations

Info

$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

INSTRUCTION SET REFERENCE Note that: • If any pair of the index, mask, or destination registers are the same, this instruction results a #UD fault. • The values may be read from memory in any order. Memory ordering with other instructions follows the Intel- 64 memory-ordering model. • Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the conventional order. • Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to the left of a faulting one may be gathered before the fault is delivered. A given implementation of this instruction is repeatable - given the same input values and architectural state, the same set of elements to the left of the faulting one will be gathered. • This instruction does not perform AC checks, and so will never deliver an AC fault. • This instruction will cause a #UD if the address size attribute is 16-bit. • This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does is implementation specific, and some implementations may use loads larger than the data element size or load elements an indeterminate number of times. • The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are ignored. Operation DEST SRC1; BASE_ADDR: base register encoded in VSIB addressing; VINDEX: the vector index register encoded by VSIB addressing; SCALE: scale factor encoded by SIB:[7:6]; DISP: optional 1, 4 byte displacement; MASK SRC3; VGATHERDPD (VEX.128 version) FOR j 0 to 1 i j * 64; IF MASK[63+i] THEN MASK[i +63:i] 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit ELSE MASK[i +63:i] 0; FI; ENDFOR FOR j 0 to 1 k j * 32; i j * 64; DATA_ADDR BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP; IF MASK[63+i] THEN DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits the instruction FI; MASK[i +63: i] 0; ENDFOR MASK[VLMAX:128] 0; DEST[VLMAX:128] 0; (non-masked elements of the mask register have the content of respective element cleared) Ref. # 319433-014 5-205
INSTRUCTION SET REFERENCE VGATHERQPD (VEX.128 version) FOR j 0 to 1 i j * 64; IF MASK[63+i] THEN MASK[i +63:i] 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit ELSE MASK[i +63:i] 0; FI; ENDFOR FOR j 0 to 1 i j * 64; DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP; IF MASK[63+i] THEN DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits this instruction FI; MASK[i +63: i] 0; ENDFOR MASK[VLMAX:128] 0; DEST[VLMAX:128] 0; (non-masked elements of the mask register have the content of respective element cleared) VGATHERQPD (VEX.256 version) FOR j 0 to 3 i j * 64; IF MASK[63+i] THEN MASK[i +63:i] 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit ELSE MASK[i +63:i] 0; FI; ENDFOR FOR j 0 to 3 i j * 64; DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP; IF MASK[63+i] THEN DEST[i +63:i] FETCH_64BITS(DATA_ADDR); // a fault exits the instruction FI; MASK[i +63: i] 0; ENDFOR (non-masked elements of the mask register have the content of respective element cleared) VGATHERDPD (VEX.256 version) FOR j 0 to 3 i j * 64; IF MASK[63+i] THEN MASK[i +63:i] 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit ELSE MASK[i +63:i] 0; FI; ENDFOR FOR j 0 to 3 k j * 32; i j * 64; DATA_ADDR BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP; IF MASK[63+i] THEN 5-206 Ref. # 319433-014
Page 1 and 2:
Intel® Architecture Instruction Se
Page 3 and 4:
CONTENTS CHAPTER 1 INTEL® ADVANCED
Page 5 and 6:
PANDN — Logical AND NOT . . . . .
Page 7 and 8:
BZHI — Zero High Bits Starting wi
Page 9 and 10:
TABLES 2-1 Rounding behavior of Zer
Page 11 and 12:
FIGURES Figure 2-1. General Procedu
Page 13 and 14:
INTEL® ADVANCED VECTOR EXTENSIONS
Page 15 and 16:
Page 17 and 18:
Page 19 and 20:
APPLICATION PROGRAMMING MODEL Prior
Page 21 and 22:
APPLICATION PROGRAMMING MODEL } and
Page 23 and 24:
APPLICATION PROGRAMMING MODEL Scala
Page 25 and 26:
APPLICATION PROGRAMMING MODEL x (mu
Page 27 and 28:
APPLICATION PROGRAMMING MODEL Instr
Page 29 and 30:
APPLICATION PROGRAMMING MODEL Table
Page 31 and 32:
APPLICATION PROGRAMMING MODEL Excep
Page 33 and 34:
APPLICATION PROGRAMMING MODEL 2.7.2
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
Page 51 and 52:
Page 53 and 54:
APPLICATION PROGRAMMING MODEL EAX 3
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
APPLICATION PROGRAMMING MODEL • T
Page 63 and 64:
APPLICATION PROGRAMMING MODEL How B
Page 65 and 66:
APPLICATION PROGRAMMING MODEL
Page 67 and 68:
APPLICATION PROGRAMMING MODEL EAX[1
Page 69 and 70:
APPLICATION PROGRAMMING MODEL EBX
Page 71 and 72:
SYSTEM PROGRAMMING MODEL • Verify
Page 73 and 74:
SYSTEM PROGRAMMING MODEL The proces
Page 75 and 76:
SYSTEM PROGRAMMING MODEL 3.3 RESET
Page 77 and 78:
INSTRUCTION FORMAT 4.1.1 VEX and th
Page 79 and 80:
INSTRUCTION FORMAT (Bit Position) 7
Page 81 and 82:
INSTRUCTION FORMAT The VEX.vvvv fie
Page 83 and 84:
INSTRUCTION FORMAT 4.1.8 The Third
Page 85 and 86:
INSTRUCTION FORMAT NOTES: 1. If Mod
Page 87 and 88:
INSTRUCTION SET REFERENCE (V)ADDSD
Page 89 and 90:
INSTRUCTION SET REFERENCE register
Page 91 and 92:
INSTRUCTION SET REFERENCE MPSADBW
Page 93 and 94:
INSTRUCTION SET REFERENCE SRC2_BYTE
Page 95 and 96:
INSTRUCTION SET REFERENCE VMPSADBW
Page 97 and 98:
INSTRUCTION SET REFERENCE DEST[79:6
Page 99 and 100:
INSTRUCTION SET REFERENCE Operation
Page 101 and 102:
INSTRUCTION SET REFERENCE PACKSSWB/
Page 103 and 104:
Page 105 and 106:
INSTRUCTION SET REFERENCE PACKUSDW
Page 107 and 108:
INSTRUCTION SET REFERENCE TMP[239:2
Page 109 and 110:
INSTRUCTION SET REFERENCE DEST[119:
Page 111 and 112:
INSTRUCTION SET REFERENCE PADDB/PAD
Page 113 and 114:
INSTRUCTION SET REFERENCE PADDQ (Le
Page 115 and 116:
INSTRUCTION SET REFERENCE PADDSB/PA
Page 117 and 118:
INSTRUCTION SET REFERENCE PADDUSB/P
Page 119 and 120:
INSTRUCTION SET REFERENCE PALIGNR
Page 121 and 122:
INSTRUCTION SET REFERENCE PAND —
Page 123 and 124:
INSTRUCTION SET REFERENCE PANDN —
Page 125 and 126:
INSTRUCTION SET REFERENCE PAVGB/PAV
Page 127 and 128:
INSTRUCTION SET REFERENCE PBLENDVB
Page 129 and 130:
INSTRUCTION SET REFERENCE IF (MASK[
Page 131 and 132:
INSTRUCTION SET REFERENCE PBLENDW
Page 133 and 134:
INSTRUCTION SET REFERENCE ELSE DEST
Page 135 and 136:
INSTRUCTION SET REFERENCE Descripti
Page 137 and 138:
INSTRUCTION SET REFERENCE PCMPEQQ (
Page 139 and 140:
Page 141 and 142:
INSTRUCTION SET REFERENCE Intel C/C
Page 143 and 144:
Page 145 and 146:
INSTRUCTION SET REFERENCE PHADDSW
Page 147 and 148:
INSTRUCTION SET REFERENCE PHSUBW/PH
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
INSTRUCTION SET REFERENCE PMADDUBSW
Page 155 and 156:
INSTRUCTION SET REFERENCE VPMADDWD
Page 157 and 158:
INSTRUCTION SET REFERENCE VEX.128 e
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
INSTRUCTION SET REFERENCE VPMINUD (
Page 173 and 174:
INSTRUCTION SET REFERENCE PMOVMSKB
Page 175 and 176:
INSTRUCTION SET REFERENCE Opcode/ I
Page 177 and 178:
INSTRUCTION SET REFERENCE VPMOVSXWQ
Page 179 and 180:
INSTRUCTION SET REFERENCE PMOVZX
Page 181 and 182:
INSTRUCTION SET REFERENCE Packed_Ze
Page 183 and 184:
INSTRUCTION SET REFERENCE Other Exc
Page 185 and 186:
Page 187 and 188:
INSTRUCTION SET REFERENCE temp13[31
Page 189 and 190:
INSTRUCTION SET REFERENCE PMULHUW
Page 191 and 192:
INSTRUCTION SET REFERENCE Intel C/C
Page 193 and 194:
Page 195 and 196:
INSTRUCTION SET REFERENCE PMULLW/PM
Page 197 and 198:
INSTRUCTION SET REFERENCE Temp10[31
Page 199 and 200:
INSTRUCTION SET REFERENCE PMULUDQ
Page 201 and 202:
INSTRUCTION SET REFERENCE POR — B
Page 203 and 204:
INSTRUCTION SET REFERENCE PSADBW
Page 205 and 206:
INSTRUCTION SET REFERENCE PSHUFB
Page 207 and 208:
INSTRUCTION SET REFERENCE PSHUFD
Page 209 and 210:
INSTRUCTION SET REFERENCE PSHUFHW
Page 211 and 212:
INSTRUCTION SET REFERENCE PSHUFLW
Page 213 and 214:
INSTRUCTION SET REFERENCE PSIGNB/PS
Page 215 and 216:
INSTRUCTION SET REFERENCE DEST[255.
Page 217 and 218:
INSTRUCTION SET REFERENCE PSLLDQ
Page 219 and 220:
INSTRUCTION SET REFERENCE PSLLW/PSL
Page 221 and 222:
Page 223 and 224:
INSTRUCTION SET REFERENCE PSLLD (xm
Page 225 and 226:
INSTRUCTION SET REFERENCE PSRAW/PSR
Page 227 and 228:
INSTRUCTION SET REFERENCE COUNT 31
Page 229 and 230:
INSTRUCTION SET REFERENCE PSRLDQ
Page 231 and 232:
INSTRUCTION SET REFERENCE PSRLW/PSR
Page 233 and 234:
INSTRUCTION SET REFERENCE FI; DEST[
Page 235 and 236:
INSTRUCTION SET REFERENCE VPSRLQ (x
Page 237 and 238:
Page 239 and 240: INSTRUCTION SET REFERENCE DEST[175:
Page 241 and 242: INSTRUCTION SET REFERENCE PSUBSB/PS
Page 243 and 244: INSTRUCTION SET REFERENCE PSUBUSB/P
Page 245 and 246: INSTRUCTION SET REFERENCE PUNPCKHBW
Page 247 and 248: INSTRUCTION SET REFERENCE DEST[95:8
Page 249 and 250: INSTRUCTION SET REFERENCE VPUNPCKHW
Page 251 and 252: INSTRUCTION SET REFERENCE Instructi
Page 253 and 254: INSTRUCTION SET REFERENCE INTERLEAV
Page 255 and 256: INSTRUCTION SET REFERENCE VPUNPCKLD
Page 257 and 258: INSTRUCTION SET REFERENCE SIMD Floa
Page 259 and 260: INSTRUCTION SET REFERENCE Operation
Page 261 and 262: INSTRUCTION SET REFERENCE VBROADCAS
Page 263 and 264: INSTRUCTION SET REFERENCE Intel C/C
Page 265 and 266: INSTRUCTION SET REFERENCE VPBLENDD
Page 269 and 270: INSTRUCTION SET REFERENCE VPBROADCA
Page 271 and 272: INSTRUCTION SET REFERENCE VPERMPD
Page 273 and 274: INSTRUCTION SET REFERENCE VPERMQ
Page 277 and 278: INSTRUCTION SET REFERENCE VINSERTI1
Page 279 and 280: INSTRUCTION SET REFERENCE The secon
Page 281 and 282: INSTRUCTION SET REFERENCE VPSLLVD/V
Page 283 and 284: INSTRUCTION SET REFERENCE Other Exc
Page 285 and 286: INSTRUCTION SET REFERENCE VPSRAVD (
Page 287 and 288: INSTRUCTION SET REFERENCE VPSRLVD (
Page 289: INSTRUCTION SET REFERENCE VGATHERDP
Page 293 and 294: INSTRUCTION SET REFERENCE VGATHERDP
Page 295 and 296: INSTRUCTION SET REFERENCE VGATHERQP
Page 297 and 298: INSTRUCTION SET REFERENCE VPGATHERD
Page 299 and 300: INSTRUCTION SET REFERENCE VPGATHERQ
Page 301 and 302: INSTRUCTION SET REFERENCE VPGATHERD
Page 303 and 304: INSTRUCTION SET REFERENCE VPGATHERQ
Page 305 and 306: INSTRUCTION SET REFERENCE This page
Page 307 and 308: INSTRUCTION SET REFERENCE - FMA VFM
Page 309 and 310: INSTRUCTION SET REFERENCE - FMA For
Page 311 and 312: INSTRUCTION SET REFERENCE - FMA sou
Page 319 and 320: INSTRUCTION SET REFERENCE - FMA Int
Page 321 and 322: INSTRUCTION SET REFERENCE - FMA the
Page 325 and 326: INSTRUCTION SET REFERENCE - FMA Int
Page 327 and 328: INSTRUCTION SET REFERENCE - FMA the
Page 331 and 332: INSTRUCTION SET REFERENCE - FMA } I
Page 333 and 334: INSTRUCTION SET REFERENCE - FMA ope
Page 339 and 340: INSTRUCTION SET REFERENCE - FMA VFN
Page 341 and 342:
INSTRUCTION SET REFERENCE - FMA Int
Page 343 and 344:
INSTRUCTION SET REFERENCE - FMA VEX
Page 345 and 346:
INSTRUCTION SET REFERENCE - FMA VFN
Page 347 and 348:
Page 349 and 350:
Page 351 and 352:
INSTRUCTION SET REFERENCE - FMA Int
Page 353 and 354:
INSTRUCTION SET REFERENCE - FMA VEX
Page 355 and 356:
Page 357 and 358:
Page 359 and 360:
INSTRUCTION SET REFERENCE - FMA Thi
Page 361 and 362:
INSTRUCTION SET REFERENCE - VEX-ENC
Page 363 and 364:
Page 365 and 366:
Page 367 and 368:
Page 369 and 370:
Page 371 and 372:
Page 373 and 374:
Page 375 and 376:
Page 377 and 378:
Page 379 and 380:
Page 381 and 382:
Page 383 and 384:
Page 385 and 386:
Page 387 and 388:
INTEL® TRANSACTIONAL SYNCHRONIZATI
Page 389 and 390:
Page 391 and 392:
Page 393 and 394:
Page 395 and 396:
Page 397 and 398:
Page 399 and 400:
Page 401 and 402:
Page 403 and 404:
Page 405 and 406:
Page 407 and 408:
ADDITIONAL NEW INSTRUCTIONS -------
Page 409 and 410:
ADDITIONAL NEW INSTRUCTIONS • If
Page 411 and 412:
ADDITIONAL NEW INSTRUCTIONS ADCX
Page 413 and 414:
ADDITIONAL NEW INSTRUCTIONS ADOX
Page 415 and 416:
ADDITIONAL NEW INSTRUCTIONS Compati
Page 417 and 418:
ADDITIONAL NEW INSTRUCTIONS Flags A
Page 419 and 420:
ADDITIONAL NEW INSTRUCTIONS STAC—
Page 421 and 422:
OPCODE MAP D The reg field of the M
Page 423 and 424:
OPCODE MAP • A ModR/M byte is req
Page 425 and 426:
OPCODE MAP A.2.5 Superscripts Utili
Page 427 and 428:
OPCODE MAP Table A-2. One-byte Opco
Page 429 and 430:
OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
Page 431 and 432:
OPCODE MAP 8 9 A B C D E F Table A-
Page 433 and 434:
OPCODE MAP 0 Table A-4. Three-byte
Page 435 and 436:
OPCODE MAP 0 66 1 66 2 66 3 4 66 5
Page 437 and 438:
OPCODE MAP A.4 OPCODE EXTENSIONS FO
Page 439 and 440:
OPCODE MAP Opcode Group Mod 7,6 pfx
Page 441 and 442:
OPCODE MAP Table A-8 shows the map
Page 443 and 444:
Page 445 and 446:
Page 447 and 448:
OPCODE MAP Table A-20 shows the opc
Page 449 and 450:
OPCODE MAP This page was intentiona
Page 451 and 452:
INSTRUCTION SUMMARY VEX.256 Encodin
Page 453 and 454:
Page 455 and 456:
Page 457 and 458:
INSTRUCTION SUMMARY Note 3: It is e
Page 459 and 460:
INSTRUCTION SUMMARY Table B-2. Prom
Page 461 and 462:
INSTRUCTION SUMMARY Table B-3. VEX-
Page 463 and 464:
INSTRUCTION SUMMARY Opcode Instruct
Page 465 and 466:
Page 467 and 468:
Page 469 and 470:
Page 471 and 472:
Page 473 and 474:
SSE extensions flag . . . . . . . .
Page 475 and 476:
SSE extensions CPUID flag . . . . .
Page 477:
I-6 Ref. # 319433-014
show all

Intel® Architecture Instruction Set Extensions Programming Reference

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?