Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

PMOVMSKB — Move Byte Mask Opcode/ <strong>Instruction</strong> Description <strong>Instruction</strong> Operand Encoding INSTRUCTION SET REFERENCE Creates a mask made up of the most significant bit of each byte of the source operand (second operand) and stores the result in the low word or dword of the destination operand (first operand). The source operand is an XMM register; the destination operand is a general-purpose register. The mask is 16-bits for 128-bit source operand and 32-bits for 256-bit source operand. The destination operand is a general-purpose register. In 64-bit mode the default operand size of the destination operand is 64 bits. Bits 63:32 are filled with zero if the source operand is a 256-bit YMM register. The upper bits above bit 15 are filled with zeros if the source operand is a 128-bit XMM register. REX.W is ignored VEX.128 encoded version: The source operand is XMM register. VEX.256 encoded version: The source operand is YMM register. Note: In VEX encoded versions VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. Operation Op/ En 64/32 -bit Mode CPUID Feature Flag VPMOVMSKB instruction with 256-bit source operand and r32: r32[0] SRC[7]; r32[1] SRC[15]; (* Repeat operation for bytes 3rd through 31*) r32[31] SRC[255]; VPMOVMSKB instruction with 256-bit source operand and r64: r64[0] SRC[7]; r64[1] SRC[15]; (* Repeat operation for bytes 2 through 31*) r64[31] SRC[255]; r64[63:32] ZERO_FILL; PMOVMSKB instruction with 128-bit source operand and r32: r32[0] SRC[7]; r32[1] SRC[15]; (* Repeat operation for bytes 2 through 14 *) r32[15] SRC[127]; r32[31:16] ZERO_FILL; Description 66 0F D7 /r A V/V SSE2 Move a 16-bit mask of xmm1 to reg. The upper bits of r32 or r64 are filled with zeros. PMOVMSKB reg, xmm1 VEX.128.66.0F.WIG D7 /r A V/V AVX Move a 16-bit mask of xmm1 to reg. The upper bits of r32 or r64 are filled with zeros. VPMOVMSKB reg, xmm1 VEX.256.66.0F.WIG D7 /r A V/V AVX2 Move a 32-bit mask of ymm1 to reg. The upper bits of r64 are filled with zeros. VPMOVMSKB reg, ymm1 Op/En Operand 1 Operand 2 Operand 3 Operand 4 A ModRM:reg (w) ModRM:r/m (r) NA NA Ref. # 319433-014 5-87
INSTRUCTION SET REFERENCE PMOVMSKB instruction with 128-bit source operand and r64: r64[0] SRC[7]; r64[1] SRC[15]; (* Repeat operation for bytes 2 through 14 *) r64[15] SRC[127]; r64[63:16] ZERO_FILL; Intel C/C++ Compiler Intrinsic Equivalent (V)PMOVMSKB: int _mm_movemask_epi8 ( __m128i a) VPMOVMSKB: int _mm256_movemask_epi8 ( __m256i a) SIMD Floating-Point Exceptions None Other Exceptions See Exceptions Type 7 5-88 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE DEST[175:
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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