Intel® Architecture Instruction Set Extensions Programming Reference

APPLICATION PROGRAMMING MODEL
2.7.11 Exception Conditions for VEX-Encoded GPR Instructions
The exception conditions applicable to VEX-encoded GPR instruction differs from those of legacy GPR instructions.
Table 2-20 groups instructions listed in Chapter 7 and lists details of the exception conditions for VEX-encoded GRP
instructions in Table 2-22 for those instructions which have a default operand size of 32 bits and 16-bit operand
size is not encodable. Table 2-21 lists exception conditions for those instructions that support operation on 16-bit
operands.
Table 2-20. Exception Groupings for Instructions Listed in Chapter 7
Exception Class Instruction
See Table 2-21 LZCNT, TZCNT
See Table 2-22 ANDN, BLSI, BLSMSK, BLSR, BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX
(*) - Additional exception restrictions are present - see the Instruction description for details
Exception
Real
Virtual 80x86
Table 2-21. Exception Definition for LZCNT and TZCNT
Protected and
Compatibility
64-bit
Cause of Exception
Stack, SS(0) X X X For an illegal address in the SS segment
X If a memory address referencing the SS segment is in a non-canonical form
General Protection,
X For an illegal memory operand effective address in the CS, DS, ES, FS or GS seg-
#GP(0)
ments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null
segment selector.
X If the memory address is in a non-canonical form.
X X If any part of the operand lies outside the effective address space from 0 to
FFFFH
Page Fault #PF(faultcode)
X X X For a page fault
Alignment Check
X X X If alignment checking is enabled and an unaligned memory reference is made
#AC(0)
while the current privilege level is 3.
2-24 Ref. # 319433-014