Intel® Architecture Instruction Set Extensions Programming Reference

SYSTEM PROGRAMMING MODEL
3.3 RESET BEHAVIOR
At processor reset
• YMM0-16 bits[255:0] are set to zero.
• XFEATURE_ENABLED_MASK[2:1] is set to zero, XFEATURE_ENABLED_MASK[0] is set to 1.
• CR4.OSXSAVE[bit 18] (and its mirror CPUID.1.ECX.OSXSAVE[bit 27]) is set to 0.
3.4 EMULATION
Setting the CR0.EMbit to 1 provides a technique to emulate Legacy SSE floating-point instruction sets in software.
This technique is not supported with AVX instructions, nor FMA instructions.
If an operating system wishes to emulate AVX instructions, set XFEATURE_ENABLED_MASK[2:1] to zero. This will
cause AVX instructions to #UD. Emulation of FMA by operating system can be done similarly as with emulating AVX
instructions.
3.5 WRITING AVX FLOATING-POINT EXCEPTION HANDLERS
AVX and FMA floating-point exceptions are handled in an entirely analogous way to Legacy SSE floating-point
exceptions. To handle unmasked SIMD floating-point exceptions, the operating system or executive must provide
an exception handler. The section titled “SSE and SSE2 SIMD Floating-Point Exceptions” in Chapter 11, “Programming
with Streaming SIMD Extensions 2 (SSE2),” of the IA-32 Intel® Architecture Software Developer’s Manual,
Volume 1, describes the SIMD floating-point exception classes and gives suggestions for writing an exception
handler to handle them.
To indicate that the operating system provides a handler for SIMD floating-point exceptions (#XM), the CR4.OSXM-
MEXCPT flag (bit 10) must be set.
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3-6 Ref. # 319433-014