Intel® Architecture Instruction Set Extensions Programming Reference

Operation
Figure 5-2. 256-bit VPALIGN Instruction Operation
PALIGNR
temp1[255:0] ((DEST[127:0] >(imm8*8);
DEST[127:0] temp1[127:0]
DEST[VLMAX:128] (Unmodified)
VPALIGNR (VEX.128 encoded version)
temp1[255:0] ((SRC1[127:0] >(imm8*8);
DEST[127:0] temp1[127:0]
DEST[VLMAX:128] 0
VPALIGNR (VEX.256 encoded version)
temp1[255:0] ((SRC1[127:0] >(imm8[7:0]*8);
DEST[127:0] temp1[127:0]
temp1[255:0] ((SRC1[255:128] >(imm8[7:0]*8);
DEST[255:128] temp1[127:0]
Intel C/C++ Compiler Intrinsic Equivalent
(V)PALIGNR: __m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)
VPALIGNR: __m256i _mm256_alignr_epi8 (__m256i a, __m256i b, const int n)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4
SRC1
127 0
127 0
Imm8[7:0]*8
255 128 255 128
SRC1
SRC2
Imm8[7:0]*8
255 128 127 0
DEST
DEST
INSTRUCTION SET REFERENCE
Ref. # 319433-014 5-35
SRC2