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Intel® Architecture Instruction Set Extensions Programming Reference

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INSTRUCTION FORMAT<br />

NOTES:<br />

1. If ModR/M.mod = 00b, the base address is zero, then effective address is computed as [scaled vector index] + disp32. Otherwise the<br />

base address is computed as [EBP/R13]+ disp, the displacement is either 8 bit or 32 bit depending on the value of ModR/M.mod:<br />

MOD Effective Address<br />

00b [Scaled Vector Register] + Disp32<br />

01b [Scaled Vector Register] + Disp8 + [EBP/R13]<br />

10b [Scaled Vector Register] + Disp32 + [EBP/R13]<br />

4.2.1 64-bit Mode VSIB Memory Addressing<br />

In 64-bit mode VSIB memory addressing uses the VEX.B field and the base field of the SIB byte to encode one of<br />

the 16 general-purpose register as the base register. The VEX.X field and the index field of the SIB byte encode one<br />

of the 16 vector registers as the vector index register.<br />

In 64-bit mode the top row of Table 4-6 base register should be interpreted as the full 64-bit of each register.<br />

4.3 VEX ENCODING SUPPORT FOR GPR INSTRUCTIONS<br />

VEX prefix may be used to encode instructions that operate on neither YMM nor XMM registers. VEX-encoded<br />

general-purpose-register instructions have the following properties:<br />

• <strong>Instruction</strong> syntax support for three encodable operands.<br />

• Encoding support for instruction syntax of non-destructive source operand, destination operand encoded via<br />

VEX.vvvv, and destructive three-operand syntax.<br />

• Elimination of escape opcode byte (0FH), two-byte escape via a compact bit field representation within the VEX<br />

prefix.<br />

• Elimination of the need to use REX prefix to encode the extended half of general-purpose register sets (R8-R15)<br />

for direct register access or memory addressing.<br />

• Flexible and more compact bit fields are provided in the VEX prefix to retain the full functionality provided by<br />

REX prefix. REX.W, REX.X, REX.B functionalities are provided in the three-byte VEX prefix only.<br />

• VEX-encoded GPR instructions are encoded with VEX.L=0.<br />

Any VEX-encoded GPR instruction with a 66H, F2H, or F3H prefix preceding VEX will #UD.<br />

Any VEX-encoded GPR instruction with a REX prefix proceeding VEX will #UD.<br />

VEX-encoded GPR instructions are not supported in real and virtual 8086 modes.<br />

§<br />

4-10 Ref. # 319433-014

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