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Intel® Architecture Instruction Set Extensions Programming Reference

Intel® Architecture Instruction Set Extensions Programming Reference

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INSTRUCTION SET REFERENCE<br />

PSADBW — Compute Sum of Absolute Differences<br />

Opcode/<br />

<strong>Instruction</strong><br />

Description<br />

<strong>Instruction</strong> Operand Encoding<br />

Computes the absolute value of the difference of packed groups of 8 unsigned byte integers from the second source<br />

operand and from the first source operand. The first 8 differences are summed to produce an unsigned word<br />

integer that is stored in the low word of the destination; the second 8 differences are summed to produce an<br />

unsigned word in bits 79:64 of the destination. In case of VEX.256 encoded version, the third group of 8 differences<br />

are summed to produce an unsigned word in bits[143:128] of the destination register and the fourth group of 8<br />

differences are summed to produce an unsigned word in bits[207:192] of the destination register. The remaining<br />

words of the destination are set to 0.<br />

128-bit Legacy SSE version: The first source operand and destination register are XMM registers. The second<br />

source operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM destination<br />

register remain unchanged.<br />

VEX.128 encoded version: The first source operand and destination register are XMM registers. The second source<br />

operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM register are<br />

zeroed.<br />

VEX.256 encoded version: The first source operand and destination register are YMM registers. The second source<br />

operand is an YMM register or a 256-bit memory location.<br />

Operation<br />

Op/<br />

En<br />

64/32<br />

-bit<br />

Mode<br />

VPSADBW (VEX.256 encoded version)<br />

TEMP0 ABS(SRC1[7:0] - SRC2[7:0])<br />

(* Repeat operation for bytes 2 through 30*)<br />

TEMP31 ABS(SRC1[255:248] - SRC2[255:248])<br />

DEST[15:0] SUM(TEMP0:TEMP7)<br />

DEST[63:16] 000000000000H<br />

DEST[79:64] SUM(TEMP8:TEMP15)<br />

DEST[127:80] 00000000000H<br />

DEST[143:128] SUM(TEMP16:TEMP23)<br />

CPUID<br />

Feature<br />

Flag<br />

Description<br />

66 0F F6 /r A V/V SSE2 Computes the absolute differences of the packed unsigned byte<br />

PSADBW xmm1, xmm2/m128<br />

integers from xmm2 /m128 and xmm1; the 8 low differences and 8<br />

high differences are then summed separately to produce two<br />

unsigned word integer results.<br />

VEX.NDS.128.66.0F.WIG F6 /r B V/V AVX Computes the absolute differences of the packed unsigned byte<br />

VPSADBW xmm1, xmm2,<br />

xmm3/m128<br />

integers from xmm3 /m128 and xmm2; the 8 low differences and 8<br />

high differences are then summed separately to produce two<br />

unsigned word integer results.<br />

VEX.NDS.256.66.0F.WIG F6 /r B V/V AVX2 Computes the absolute differences of the packed unsigned byte<br />

VPSADBW ymm1, ymm2,<br />

ymm3/m256<br />

integers from ymm3 /m256 and ymm2; then each consecutive 8 differences<br />

are summed separately to produce four unsigned word<br />

integer results.<br />

Op/En Operand 1 Operand 2 Operand 3 Operand 4<br />

A ModRM:reg (r, w) ModRM:r/m (r) NA NA<br />

B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA<br />

5-118 Ref. # 319433-014

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