Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE - FMA
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS — Fused Negative Multiply-Add of Scalar
Single-Precision Floating-Point Values
Opcode/
Instruction
VEX.DDS.LIG.128.66.0F38.W0
9D /r
VFNMADD132SS xmm0, xmm1,
xmm2/m32
VEX.DDS.LIG.128.66.0F38.W0
AD /r
VFNMADD213SS xmm0, xmm1,
xmm2/m32
VEX.DDS.LIG.128.66.0F38.W0
BD /r
VFNMADD231SS xmm0, xmm1,
xmm2/m32
Description
Instruction Operand Encoding
VFNMADD132SS: Multiplies the low packed single-precision floating-point value from the first source operand to
the low packed single-precision floating-point value in the third source operand, adds the negated infinite precision
intermediate result to the low packed single-precision floating-point value in the second source operand, performs
rounding and stores the resulting packed single-precision floating-point value to the destination operand (first
source operand).
VFNMADD213SS: Multiplies the low packed single-precision floating-point value from the second source operand to
the low packed single-precision floating-point value in the first source operand, adds the negated infinite precision
intermediate result to the low packed single-precision floating-point value in the third source operand, performs
rounding and stores the resulting packed single-precision floating-point value to the destination operand (first
source operand).
VFNMADD231SS: Multiplies the low packed single-precision floating-point value from the second source operand to
the low packed single-precision floating-point value in the third source operand, adds the negated infinite precision
intermediate result to the low packed single-precision floating-point value in the first source operand, performs
rounding and stores the resulting packed single-precision floating-point value to the destination operand (first
source operand).
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 32-bit memory location and encoded in rm_field. The upper bits ([255:128]) of the YMM destination
register are zeroed.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column. See also Section 2.3.1, “FMA Instruction Operand Order and Arithmetic Behavior”.
Operation
Op/
En
64/32
-bit
Mode
CPUID
Feature
Flag
Description
A V/V FMA Multiply scalar single-precision floating-point value from xmm0 and
xmm2/mem, negate the multiplication result and add to xmm1 and
put result in xmm0.
A V/V FMA Multiply scalar single-precision floating-point value from xmm0 and
xmm1, negate the multiplication result and add to xmm2/mem and
put result in xmm0.
A V/V FMA Multiply scalar single-precision floating-point value from xmm1 and
xmm2/mem, negate the multiplication result and add to xmm0 and
put result in xmm0.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) NA
In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
6-42 Ref. # 319433-014