Intel® Architecture Instruction Set Extensions Programming Reference

DEST[111:96] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 ABS(SRC1_BYTE8 - SRC2_BYTE1)
TEMP2 ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 ABS(SRC1_BYTE10 - SRC2_BYTE3)
DEST[127:112] TEMP0 + TEMP1 + TEMP2 + TEMP3
DEST[VLMAX:128] 0
MPSADBW (128-bit Legacy SSE version)
SRC_OFFSET imm8[1:0]*32
DEST_OFFSET imm8[2]*32
DEST_BYTE0 DEST[DEST_OFFSET+7:DEST_OFFSET]
DEST_BYTE1 DEST[DEST_OFFSET+15:DEST_OFFSET+8]
DEST_BYTE2 DEST[DEST_OFFSET+23:DEST_OFFSET+16]
DEST_BYTE3 DEST[DEST_OFFSET+31:DEST_OFFSET+24]
DEST_BYTE4 DEST[DEST_OFFSET+39:DEST_OFFSET+32]
DEST_BYTE5 DEST[DEST_OFFSET+47:DEST_OFFSET+40]
DEST_BYTE6 DEST[DEST_OFFSET+55:DEST_OFFSET+48]
DEST_BYTE7 DEST[DEST_OFFSET+63:DEST_OFFSET+56]
DEST_BYTE8 DEST[DEST_OFFSET+71:DEST_OFFSET+64]
DEST_BYTE9 DEST[DEST_OFFSET+79:DEST_OFFSET+72]
DEST_BYTE10 DEST[DEST_OFFSET+87:DEST_OFFSET+80]
SRC_BYTE0 SRC[SRC_OFFSET+7:SRC_OFFSET]
SRC_BYTE1 SRC[SRC_OFFSET+15:SRC_OFFSET+8]
SRC_BYTE2 SRC[SRC_OFFSET+23:SRC_OFFSET+16]
SRC_BYTE3 SRC[SRC_OFFSET+31:SRC_OFFSET+24]
TEMP0 ABS(DEST_BYTE0 - SRC_BYTE0)
TEMP1 ABS(DEST_BYTE1 - SRC_BYTE1)
TEMP2 ABS(DEST_BYTE2 - SRC_BYTE2)
TEMP3 ABS(DEST_BYTE3 - SRC_BYTE3)
DEST[15:0] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(DEST_BYTE1 - SRC_BYTE0)
TEMP1 ABS(DEST_BYTE2 - SRC_BYTE1)
TEMP2 ABS(DEST_BYTE3 - SRC_BYTE2)
TEMP3 ABS(DEST_BYTE4 - SRC_BYTE3)
DEST[31:16] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(DEST_BYTE2 - SRC_BYTE0)
TEMP1 ABS(DEST_BYTE3 - SRC_BYTE1)
TEMP2 ABS(DEST_BYTE4 - SRC_BYTE2)
TEMP3 ABS(DEST_BYTE5 - SRC_BYTE3)
DEST[47:32] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(DEST_BYTE3 - SRC_BYTE0)
TEMP1 ABS(DEST_BYTE4 - SRC_BYTE1)
TEMP2 ABS(DEST_BYTE5 - SRC_BYTE2)
TEMP3 ABS(DEST_BYTE6 - SRC_BYTE3)
DEST[63:48] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(DEST_BYTE4 - SRC_BYTE0)
TEMP1 ABS(DEST_BYTE5 - SRC_BYTE1)
TEMP2 ABS(DEST_BYTE6 - SRC_BYTE2)
TEMP3 ABS(DEST_BYTE7 - SRC_BYTE3)
INSTRUCTION SET REFERENCE
Ref. # 319433-014 5-11