Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
register with individual elements of 32-bit index value. The vector index register is an XMM register if expressed
as vm32x. The vector index register is a YMM register if expressed as vm32y.
• vm64x,vm64y — A vector array of memory operands specified using VSIB memory addressing. The array of
memory addresses are specified using a common base register, a constant scale factor, and a vector index
register with individual element of 64-bit index value. The vector index register is an XMM register if expressed
as vm64x. The vector index register is a YMM register if expressed as vm64y.
• ymm/m256 — A YMM register or 256-bit memory operand.
• — Indicates use of the YMM0 register as an implicit argument.
• SRC1 — Denotes the first source operand in the instruction syntax of an instruction encoded with the VEX
prefix and having two or more source operands.
• SRC2 — Denotes the second source operand in the instruction syntax of an instruction encoded with the VEX
prefix and having two or more source operands.
• SRC3 — Denotes the third source operand in the instruction syntax of an instruction encoded with the VEX
prefix and having three source operands.
• SRC — The source in a AVX single-source instruction or the source in a Legacy SSE instruction.
• DST — the destination in a AVX instruction. In Legacy SSE instructions can be either the destination, first
source, or both. This field is encoded by reg_field.
5.1.4 Operand Encoding column in the Instruction Summary Table
The “operand encoding” column is abbreviated as Op/En in the Instruction Summary table heading. Each entry
corresponds to a specific instruction syntax in the immediate column to its left and points to a corresponding row
in a separate instruction operand encoding table immediately following the instruction summary table. The operand
encoding table in each instruction reference page lists each instruction operand (according to each instruction
syntax and operand ordering shown in the instruction column) relative to the ModRM byte, VEX.vvvv field or additional
operand encoding placement.
5.1.5 64/32 bit Mode Support column in the Instruction Summary Table
The “64/32 bit Mode Support” column in the Instruction Summary table indicates whether an opcode sequence is
supported in (a) 64-bit mode or (b) the Compatibility mode and other IA-32 modes that apply in conjunction with
the CPUID feature flag associated specific instruction extensions.
The 64-bit mode support is to the left of the ‘slash’ and has the following notation:
• V — Supported.
• I — Not supported.
• N.E. — Indicates an instruction syntax is not encodable in 64-bit mode (it may represent part of a sequence
of valid instructions in other modes).
• N.P. — Indicates the REX prefix does not affect the legacy instruction in 64-bitmode.
• N.I. — Indicates the opcode is treated as a new instruction in 64-bit mode.
• N.S. — Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not supported.
Using an address override prefix in 64-bit mode may result in model-specific execution behavior.
The compatibility/Legacy mode support is to the right of the ‘slash’ and has the following notation:
• V — Supported.
• I — Not supported.
• N.E. — Indicates an Intel 64 instruction mnemonics/syntax that is not encodable; the opcode sequence is not
applicable as an individual instruction in compatibility mode or IA-32 mode. The opcode may represent a valid
sequence of legacy IA-32 instructions.
5-4 Ref. # 319433-014