Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS
PDEP — Parallel Bits Deposit
Opcode/Instruction Op/
En
Description
Instruction Operand Encoding
PDEP uses a mask in the second source operand (the third operand) to transfer/scatter contiguous low order bits
in the first source operand (the second operand) into the destination (the first operand). PDEP takes the low bits
from the first source operand and deposit them in the destination operand at the corresponding bit locations that
are set in the second source operand (mask). All other bits (bits not set in mask) in destination are set to zero.
Figure 7-1. PDEP Example
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
TEMP ← SRC1;
MASK ← SRC2;
DEST ← 0 ;
m← 0, k← 0;
DO WHILE m< OperandSize
IF MASK[ m] = 1 THEN
DEST[ m] ← TEMP[ k];
k ← k+ 1;
FI
m ← m+ 1;
64/32
-bit
Mode
CPUID
Feature
Flag
Description
VEX.NDS.LZ.F2.0F38.W0 F5 /r A V/V BMI2 Parallel deposit of bits from r32b using mask in r/m32, result is written
to r32a.
PDEP r32a, r32b, r/m32
VEX.NDS.LZ.F2.0F38.W1 F5 /r A V/N.E. BMI2 Parallel deposit of bits from r64b using mask in r/m64, result is written
to r64a
PDEP r64a, r64b, r/m64
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
SRC1
SRC2
(mask)
DEST
S31 S30 S29 S28 S27 S7 S6 S5 S4 S3 S2 S1 S0 0
0
0 0
bit 31
0
0
1
S 3
0
0
7-14 Ref. # 319433-014
1
S 2
0
0
1
S 1
0
0
0
0
1
S 0
0
0
0
0
bit 0