Intel® Architecture Instruction Set Extensions Programming Reference

APPLICATION PROGRAMMING MODEL
Instruction Type
AVX, FMA, AVX2,
SSE
Table 2-3. Alignment Faulting Conditions when Memory Access is Not Aligned
EFLAGS.AC==1 && Ring-3 && CR0.AM == 1 0 1
16- or 32-byte “explicitly unaligned” loads and stores (see Table 2-5) no fault no fault
VEX op YMM, m256 no fault no fault
VEX op XMM, m128 no fault no fault
“explicitly aligned” loads and stores (see Table 2-4) #GP(0) #GP(0)
2, 4, or 8-byte loads and stores no fault #AC(0)
16 byte “explicitly unaligned” loads and stores (see Table 2-5) no fault no fault
op XMM, m128 #GP(0) #GP(0)
“explicitly aligned” loads and stores (see Table 2-4) #GP(0) #GP(0)
2, 4, or 8-byte loads and stores no fault #AC(0)
Table 2-4. Instructions Requiring Explicitly Aligned Memory
Require 16-byte alignment Require 32-byte alignment
(V)MOVDQA xmm, m128 VMOVDQA ymm, m256
(V)MOVDQA m128, xmm VMOVDQA m256, ymm
(V)MOVAPS xmm, m128 VMOVAPS ymm, m256
(V)MOVAPS m128, xmm VMOVAPS m256, ymm
(V)MOVAPD xmm, m128 VMOVAPD ymm, m256
(V)MOVAPD m128, xmm VMOVAPD m256, ymm
(V)MOVNTPS m128, xmm VMOVNTPS m256, ymm
(V)MOVNTPD m128, xmm VMOVNTPD m256, ymm
(V)MOVNTDQ m128, xmm VMOVNTDQ m256, ymm
(V)MOVNTDQA xmm, m128 VMOVNTDQA ymm, m256
(V)MOVDQU xmm, m128
(V)MOVDQU m128, m128
(V)MOVUPS xmm, m128
(V)MOVUPS m128, xmm
(V)MOVUPD xmm, m128
(V)MOVUPD m128, xmm
VMOVDQU ymm, m256
VMOVDQU m256, ymm
VMOVUPS ymm, m256
VMOVUPS m256, ymm
VMOVUPD ymm, m256
VMOVUPD m256, ymm
Table 2-5. Instructions Not Requiring Explicit Memory Alignment
2-10 Ref. # 319433-014