Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS
BLSMSK — Get Mask Up to Lowest Set Bit
Opcode/Instruction Op/
En
Description
Instruction Operand Encoding
Sets all the lower bits of the destination operand to “1” up to and including lowest set bit (=1) in the source
operand. If source operand is zero, BLSMSK sets all bits of the destination operand to 1 and also sets CF to 1.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
temp ← (SRC-1) XOR (SRC) ;
SF ← temp[OperandSize -1];
ZF ← 0;
IF SRC = 0
CF ← 1;
ELSE
CF ← 0;
FI
DEST ← temp;
Flags Affected
SF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are
undefined.
Intel C/C++ Compiler Intrinsic Equivalent
BLSMSK: unsigned __int32 _blsmsk_u32(unsigned __int32 src);
BLSMSK: unsigned __int64 _blsmsk_u64(unsigned __int64 src);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-22.
64/32
-bit
Mode
CPUID
Feature
Flag
Description
VEX.NDD.LZ.0F38.W0 F3 /2 A V/V BMI1 Set all lower bits in r32 to “1” starting from bit 0 to lowest set bit in
r/m32.
BLSMSK r32, r/m32
VEX.NDD.LZ.0F38.W1 F3 /2 A V/N.E. BMI1 Set all lower bits in r64 to “1” starting from bit 0 to lowest set bit in
r/m64.
BLSMSK r64, r/m64
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A VEX.vvvv (w) ModRM:r/m (r) NA NA
7-6 Ref. # 319433-014