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Intel® Architecture Instruction Set Extensions Programming Reference

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APPLICATION PROGRAMMING MODEL<br />

Table 2-23. Information Returned by CPUID <strong>Instruction</strong>(Continued)<br />

Initial EAX<br />

Value Information Provided about the Processor<br />

EDX Bits 03 - 00: Number of C0* sub C-states supported using MWait<br />

Bits 07 - 04: Number of C1* sub C-states supported using MWAIT<br />

Bits 11 - 08: Number of C2* sub C-states supported using MWAIT<br />

Bits 15 - 12: Number of C3* sub C-states supported using MWAIT<br />

Bits 19 - 16: Number of C4* sub C-states supported using MWAIT<br />

Bits 31 - 20: Reserved = 0<br />

NOTE:<br />

* The definition of C0 through C4 states for MWAIT extension are processor-specific C-states, not<br />

ACPI C-states.<br />

Thermal and Power Management Leaf<br />

06H EAX<br />

Bits 00: Digital temperature sensor is supported if set<br />

Bits 01: Intel Turbo Boost Technology is available<br />

Bits 31 - 02: Reserved<br />

EBX<br />

Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor<br />

Bits 31 - 04: Reserved<br />

ECX Bits 00: Hardware Coordination Feedback Capability (Presence of MCNT and ACNT MSRs). The capability<br />

to provide a measure of delivered processor performance (since last reset of the counters), as a<br />

percentage of expected processor performance at frequency specified in CPUID Brand String<br />

Bits 02 - 01: Reserved = 0<br />

Bit 03: The processor supports performance-energy bias preference if<br />

CPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of a<br />

new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H)<br />

Bits 31 - 04: Reserved = 0<br />

EDX Reserved = 0<br />

07H<br />

Structured Extended feature Leaf<br />

NOTES:<br />

Leaf 07H main leaf (ECX = 0).<br />

IF leaf 07H is not supported, EAX=EBX=ECX=EDX=0<br />

EAX Bits 31-0: Reports the maximum number sub-leaves that are supported in leaf 07H.<br />

EBX Bit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.<br />

Bits 02-01: Reserved<br />

Bit 03: BMI1<br />

Bit 04: HLE<br />

Bit 05: AVX2<br />

Bit 07: SMEP. Supports Supervisor Mode Execution Protection if 1.<br />

Bit 06: Reserved<br />

Bit 08: BMI2<br />

Bit 09: ERMS<br />

Bit 10: INVPCID<br />

Bit 11: RTM<br />

Bits 17-12: Reserved<br />

Bit 18: RDSEED<br />

Bit 19: ADX<br />

Bit 20: SMAP<br />

Bits 31-21: Reserved<br />

ECX Bit 31-0: Reserved<br />

EDX Bit 31-0: Reserved.<br />

Structured Extended Feature Enumeration Sub-leaves (EAX = 07H, ECX = n, n > 1)<br />

2-30 Ref. # 319433-014

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