Intel® Architecture Instruction Set Extensions Programming Reference

PHADDW/PHADDD — Packed Horizontal Add
Opcode/
Instruction
Description
Op/
En
64/32
-bit
Mode
CPUID
Feature
Flag
Description
Instruction Operand Encoding
INSTRUCTION SET REFERENCE
66 0F 38 01 /r A V/V SSSE3 Add 16-bit signed integers horizontally, pack to xmm1.
PHADDW xmm1, xmm2/m128
66 0F 38 02 /r A V/V SSSE3 Add 32-bit signed integers horizontally, pack to xmm1.
PHADDD xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 01 /r B V/V AVX Add 16-bit signed integers horizontally, pack to xmm1.
VPHADDW xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.WIG 02 /r B V/V AVX Add 32-bit signed integers horizontally, pack to xmm1.
VPHADDD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.WIG 01 /r B V/V AVX2 Add 16-bit signed integers horizontally, pack to ymm1.
VPHADDW ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.WIG 02 /r B V/V AVX2 Add 32-bit signed integers horizontally, pack to ymm1.
VPHADDD ymm1, ymm2,
ymm3/m256
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA
(V)PHADDW adds two adjacent 16-bit signed integers horizontally from the second source operand and the first
source operand and packs the 16-bit signed results to the destination operand. (V)PHADDD adds two adjacent 32bit
signed integers horizontally from the second source operand and the first source operand and packs the 32-bit
signed results to the destination operand. The first source and destination operands are XMM registers. The second
source operand is an XMM register or a 128-bit memory location.
Legacy SSE instructions: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. In 64-bit mode use the REX prefix to access additional
registers.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (255:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (255:128) of the corresponding YMM register are
zeroed.
VEX.256 encoded version: Horizontal addition of two adjacent data elements of the low 16-bytes of the first and
second source operands are packed into the low 16-bytes of the destination operand. Horizontal addition of two
adjacent data elements of the high 16-bytes of the first and second source operands are packed into the high 16bytes
of the destination operand. The second source operand can be an YMM register or a 256-bit memory location.
The first source and destination operands are YMM registers.
Ref. # 319433-014 5-57