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Intel® Architecture Instruction Set Extensions Programming Reference

Intel® Architecture Instruction Set Extensions Programming Reference

Intel® Architecture Instruction Set Extensions Programming Reference

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INSTRUCTION SET REFERENCE<br />

SRC2_BYTE0 SRC2[SRC2_OFFSET+7:SRC2_OFFSET]<br />

SRC2_BYTE1 SRC2[SRC2_OFFSET+15:SRC2_OFFSET+8]<br />

SRC2_BYTE2 SRC2[SRC2_OFFSET+23:SRC2_OFFSET+16]<br />

SRC2_BYTE3 SRC2[SRC2_OFFSET+31:SRC2_OFFSET+24]<br />

TEMP0 ABS(SRC1_BYTE0 - SRC2_BYTE0)<br />

TEMP1 ABS(SRC1_BYTE1 - SRC2_BYTE1)<br />

TEMP2 ABS(SRC1_BYTE2 - SRC2_BYTE2)<br />

TEMP3 ABS(SRC1_BYTE3 - SRC2_BYTE3)<br />

DEST[15:0] TEMP0 + TEMP1 + TEMP2 + TEMP3<br />

TEMP0 ABS(SRC1_BYTE1 - SRC2_BYTE0)<br />

TEMP1 ABS(SRC1_BYTE2 - SRC2_BYTE1)<br />

TEMP2 ABS(SRC1_BYTE3 - SRC2_BYTE2)<br />

TEMP3 ABS(SRC1_BYTE4 - SRC2_BYTE3)<br />

DEST[31:16] TEMP0 + TEMP1 + TEMP2 + TEMP3<br />

TEMP0 ABS(SRC1_BYTE2 - SRC2_BYTE0)<br />

TEMP1 ABS(SRC1_BYTE3 - SRC2_BYTE1)<br />

TEMP2 ABS(SRC1_BYTE4 - SRC2_BYTE2)<br />

TEMP3 ABS(SRC1_BYTE5 - SRC2_BYTE3)<br />

DEST[47:32] TEMP0 + TEMP1 + TEMP2 + TEMP3<br />

TEMP0 ABS(SRC1_BYTE3 - SRC2_BYTE0)<br />

TEMP1 ABS(SRC1_BYTE4 - SRC2_BYTE1)<br />

TEMP2 ABS(SRC1_BYTE5 - SRC2_BYTE2)<br />

TEMP3 ABS(SRC1_BYTE6 - SRC2_BYTE3)<br />

DEST[63:48] TEMP0 + TEMP1 + TEMP2 + TEMP3<br />

TEMP0 ABS(SRC1_BYTE4 - SRC2_BYTE0)<br />

TEMP1 ABS(SRC1_BYTE5 - SRC2_BYTE1)<br />

TEMP2 ABS(SRC1_BYTE6 - SRC2_BYTE2)<br />

TEMP3 ABS(SRC1_BYTE7 - SRC2_BYTE3)<br />

DEST[79:64] TEMP0 + TEMP1 + TEMP2 + TEMP3<br />

TEMP0 ABS(SRC1_BYTE5 - SRC2_BYTE0)<br />

TEMP1 ABS(SRC1_BYTE6 - SRC2_BYTE1)<br />

TEMP2 ABS(SRC1_BYTE7 - SRC2_BYTE2)<br />

TEMP3 ABS(SRC1_BYTE8 - SRC2_BYTE3)<br />

DEST[95:80] TEMP0 + TEMP1 + TEMP2 + TEMP3<br />

TEMP0 ABS(SRC1_BYTE6 - SRC2_BYTE0)<br />

TEMP1 ABS(SRC1_BYTE7 - SRC2_BYTE1)<br />

TEMP2 ABS(SRC1_BYTE8 - SRC2_BYTE2)<br />

TEMP3 ABS(SRC1_BYTE9 - SRC2_BYTE3)<br />

DEST[111:96] TEMP0 + TEMP1 + TEMP2 + TEMP3<br />

TEMP0 ABS(SRC1_BYTE7 - SRC2_BYTE0)<br />

TEMP1 ABS(SRC1_BYTE8 - SRC2_BYTE1)<br />

TEMP2 ABS(SRC1_BYTE9 - SRC2_BYTE2)<br />

TEMP3 ABS(SRC1_BYTE10 - SRC2_BYTE3)<br />

DEST[127:112] TEMP0 + TEMP1 + TEMP2 + TEMP3<br />

SRC2_OFFSET imm8[4:3]*32 + 128<br />

SRC1_OFFSET imm8[5]*32 + 128<br />

SRC1_BYTE0 SRC1[SRC1_OFFSET+7:SRC1_OFFSET]<br />

SRC1_BYTE1 SRC1[SRC1_OFFSET+15:SRC1_OFFSET+8]<br />

SRC1_BYTE2 SRC1[SRC1_OFFSET+23:SRC1_OFFSET+16]<br />

SRC1_BYTE3 SRC1[SRC1_OFFSET+31:SRC1_OFFSET+24]<br />

SRC1_BYTE4 SRC1[SRC1_OFFSET+39:SRC1_OFFSET+32]<br />

5-8 Ref. # 319433-014

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