Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

B.1 AVX INSTRUCTIONS INSTRUCTION SUMMARY APPENDIX B INSTRUCTION SUMMARY In AVX, most SSE/SSE2/SSE3/SSSE3/SSE4 Instructions have been promoted to support VEX.128 encodings which, for non-memory-store versions implies support for zeroing upper bits of YMM registers. Table B-1 summarizes the promotion status for existing instructions. The column “VEX.256” indicates whether 256-bit vector form of the instruction using the VEX.256 prefix encoding is supported. The column “VEX.128” indicates whether the instruction using VEX.128 prefix encoding is supported. VEX.256 Encoding VEX.128 Encoding Table B-1. Promoted SSE/SSE2/SSE3/SSSE3/SSE4 Instructions in AVX Group Instruction If No, Reason? yes yes YY 0F 1X MOVUPS no yes MOVSS scalar yes yes MOVUPD no yes MOVSD scalar no yes MOVLPS Note 1 no yes MOVLPD Note 1 no yes MOVLHPS Redundant with VPERMILPS yes yes MOVDDUP yes yes MOVSLDUP yes yes UNPCKLPS yes yes UNPCKLPD yes yes UNPCKHPS yes yes UNPCKHPD no yes MOVHPS Note 1 no yes MOVHPD Note 1 no yes MOVHLPS Redundant with VPERMILPS yes yes MOVAPS yes yes MOVSHDUP yes yes MOVAPD no no CVTPI2PS MMX no yes CVTSI2SS scalar no no CVTPI2PD MMX no yes CVTSI2SD scalar yes yes MOVNTPS yes yes MOVNTPD no no CVTTPS2PI MMX no yes CVTTSS2SI scalar no no CVTTPD2PI MMX Ref. # 319433-014 B-1
INSTRUCTION SUMMARY VEX.256 Encoding VEX.128 Encoding Table B-1. Promoted SSE/SSE2/SSE3/SSSE3/SSE4 Instructions in AVX Group Instruction If No, Reason? no yes CVTTSD2SI scalar no no CVTPS2PI MMX no yes CVTSS2SI scalar no no CVTPD2PI MMX no yes CVTSD2SI scalar no yes UCOMISS scalar no yes UCOMISD scalar no yes COMISS scalar no yes COMISD scalar yes yes YY 0F 5X MOVMSKPS yes yes MOVMSKPD yes yes SQRTPS no yes SQRTSS scalar yes yes SQRTPD no yes SQRTSD scalar yes yes RSQRTPS no yes RSQRTSS scalar yes yes RCPPS no yes RCPSS scalar yes yes ANDPS yes yes ANDPD yes yes ANDNPS yes yes ANDNPD yes yes ORPS yes yes ORPD yes yes XORPS yes yes XORPD yes yes ADDPS no yes ADDSS scalar yes yes ADDPD no yes ADDSD scalar yes yes MULPS no yes MULSS scalar yes yes MULPD no yes MULSD scalar yes yes CVTPS2PD no yes CVTSS2SD scalar yes yes CVTPD2PS B-2 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE ELSE DEST
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PCMPEQQ (
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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Page 399 and 400: INTEL® TRANSACTIONAL SYNCHRONIZATI
Page 407 and 408: ADDITIONAL NEW INSTRUCTIONS -------
Page 409 and 410: ADDITIONAL NEW INSTRUCTIONS • If
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Page 421 and 422: OPCODE MAP D The reg field of the M
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Page 429 and 430: OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
Page 431 and 432: OPCODE MAP 8 9 A B C D E F Table A-
Page 433 and 434: OPCODE MAP 0 Table A-4. Three-byte
Page 435 and 436: OPCODE MAP 0 66 1 66 2 66 3 4 66 5
Page 437 and 438: OPCODE MAP A.4 OPCODE EXTENSIONS FO
Page 439 and 440: OPCODE MAP Opcode Group Mod 7,6 pfx
Page 441 and 442: OPCODE MAP Table A-8 shows the map
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Page 453 and 454: INSTRUCTION SUMMARY VEX.256 Encodin
Page 455 and 456: INSTRUCTION SUMMARY VEX.256 Encodin
Page 457 and 458: INSTRUCTION SUMMARY Note 3: It is e
Page 459 and 460: INSTRUCTION SUMMARY Table B-2. Prom
Page 461 and 462: INSTRUCTION SUMMARY Table B-3. VEX-
Page 463 and 464: INSTRUCTION SUMMARY Opcode Instruct
Page 473 and 474: SSE extensions flag . . . . . . . .
Page 475 and 476: SSE extensions CPUID flag . . . . .
Page 477: I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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