Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SUMMARY
Opcode Instruction Description
F3 0F BC /r TZCNT r16, r/m16 Count the number of trailing zero bits in r/m16, return result in
r16
F3 0F BC /r TZCNT r32, r/m32 Count the number of trailing zero bits in r/m32, return result in
r32
REX.W + F3 0F BC /r TZCNT r64, r/m64 Count the number of trailing zero bits in r/m64, return result in
r64.
66 0F 38 82 /r INVPCID r32, m128 Invalidates entries in the TLBs and paging-structure caches
based on invalidation type in r32 and descriptor in m128.
66 0F 38 82 /r INVPCID r64, m128 Invalidates entries in the TLBs and paging-structure caches
based on invalidation type in r64 and descriptor in m128.
Table B-7. New Instructions Introduced in Processors Based on Intel Microarchitecture Code Name Ivy Bridge
Opcode Instruction Description
F3 0F AE /0 RDFSBASE r32 Read FS base register and place the 32-bit result in
the destination register.
REX.W + F3 0F AE /0 RDFSBASE r64 Read FS base register and place the 64-bit result in
the destination register.
F3 0F AE /1 RDGSBASE r32 Read GS base register and place the 32-bit result in
destination register.
REX.W + F3 0F AE /1 RDGSBASE r64 Read GS base register and place the 64-bit result in
destination register.
0F C7 /6 RDRAND r16 Read a 16-bit random number and store in the destination
register.
0F C7 /6 RDRAND r32 Read a 32-bit random number and store in the destination
register.
REX.W + 0F C7 /6 RDRAND r64 Read a 64-bit random number and store in the destination
register.
F3 0F AE /2 WRFSBASE r32 Write the 32-bit value in the source register to FS
base register.
REX.W + F3 0F AE /2 WRFSBASE r64 Write the 64-bit value in the source register to FS
base register.
F3 0F AE /3 WRGSBASE r32 Write the 32-bit value in the source register to GS
base register.
REX.W + F3 0F AE /3 WRGSBASE r64 Write the 64-bit value in the source register to GS
base register.
VEX.256.66.0F38.W0 13 /r VCVTPH2PS ymm1, xmm2/m128 Convert eight packed half precision (16-bit) floatingpoint
values in xmm2/m128 to packed single-precision
floating-point value in ymm1.
VEX.128.66.0F38.W0 13 /r VCVTPH2PS xmm1, xmm2/m64 Convert four packed half precision (16-bit) floatingpoint
values in xmm2/m64 to packed single-precision
floating-point value in xmm1.
VEX.256.66.0F3A.W0 1D /r ib VCVTPS2PH xmm1/m128, ymm2, imm8 Convert eight packed single-precision floating-point
value in ymm2 to packed half-precision (16-bit)
floating-point value in xmm1/mem. Imm8 provides
rounding controls.
VEX.128.66.0F3A.W0.1D /r ib VCVTPS2PH xmm1/m64, xmm2, imm8 Convert four packed single-precision floating-point
value in xmm2 to packed half-precision (16-bit)
floating-point value in xmm1/mem. Imm8 provides
rounding controls.
B-22 Ref. # 319433-014