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Intel® Architecture Instruction Set Extensions Programming Reference

Intel® Architecture Instruction Set Extensions Programming Reference

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INSTRUCTION SUMMARY<br />

Opcode <strong>Instruction</strong> Description<br />

F3 0F BC /r TZCNT r16, r/m16 Count the number of trailing zero bits in r/m16, return result in<br />

r16<br />

F3 0F BC /r TZCNT r32, r/m32 Count the number of trailing zero bits in r/m32, return result in<br />

r32<br />

REX.W + F3 0F BC /r TZCNT r64, r/m64 Count the number of trailing zero bits in r/m64, return result in<br />

r64.<br />

66 0F 38 82 /r INVPCID r32, m128 Invalidates entries in the TLBs and paging-structure caches<br />

based on invalidation type in r32 and descriptor in m128.<br />

66 0F 38 82 /r INVPCID r64, m128 Invalidates entries in the TLBs and paging-structure caches<br />

based on invalidation type in r64 and descriptor in m128.<br />

Table B-7. New <strong>Instruction</strong>s Introduced in Processors Based on Intel Microarchitecture Code Name Ivy Bridge<br />

Opcode <strong>Instruction</strong> Description<br />

F3 0F AE /0 RDFSBASE r32 Read FS base register and place the 32-bit result in<br />

the destination register.<br />

REX.W + F3 0F AE /0 RDFSBASE r64 Read FS base register and place the 64-bit result in<br />

the destination register.<br />

F3 0F AE /1 RDGSBASE r32 Read GS base register and place the 32-bit result in<br />

destination register.<br />

REX.W + F3 0F AE /1 RDGSBASE r64 Read GS base register and place the 64-bit result in<br />

destination register.<br />

0F C7 /6 RDRAND r16 Read a 16-bit random number and store in the destination<br />

register.<br />

0F C7 /6 RDRAND r32 Read a 32-bit random number and store in the destination<br />

register.<br />

REX.W + 0F C7 /6 RDRAND r64 Read a 64-bit random number and store in the destination<br />

register.<br />

F3 0F AE /2 WRFSBASE r32 Write the 32-bit value in the source register to FS<br />

base register.<br />

REX.W + F3 0F AE /2 WRFSBASE r64 Write the 64-bit value in the source register to FS<br />

base register.<br />

F3 0F AE /3 WRGSBASE r32 Write the 32-bit value in the source register to GS<br />

base register.<br />

REX.W + F3 0F AE /3 WRGSBASE r64 Write the 64-bit value in the source register to GS<br />

base register.<br />

VEX.256.66.0F38.W0 13 /r VCVTPH2PS ymm1, xmm2/m128 Convert eight packed half precision (16-bit) floatingpoint<br />

values in xmm2/m128 to packed single-precision<br />

floating-point value in ymm1.<br />

VEX.128.66.0F38.W0 13 /r VCVTPH2PS xmm1, xmm2/m64 Convert four packed half precision (16-bit) floatingpoint<br />

values in xmm2/m64 to packed single-precision<br />

floating-point value in xmm1.<br />

VEX.256.66.0F3A.W0 1D /r ib VCVTPS2PH xmm1/m128, ymm2, imm8 Convert eight packed single-precision floating-point<br />

value in ymm2 to packed half-precision (16-bit)<br />

floating-point value in xmm1/mem. Imm8 provides<br />

rounding controls.<br />

VEX.128.66.0F3A.W0.1D /r ib VCVTPS2PH xmm1/m64, xmm2, imm8 Convert four packed single-precision floating-point<br />

value in xmm2 to packed half-precision (16-bit)<br />

floating-point value in xmm1/mem. Imm8 provides<br />

rounding controls.<br />

B-22 Ref. # 319433-014

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