Intel® Architecture Instruction Set Extensions Programming Reference

APPLICATION PROGRAMMING MODEL
x
(multiplicand)
y
(multiplier)
F 0 F z -z z -z
F F 0 x*y x*y -x*y -x*y Rounded to the destination precision, with
bounded exponent
F F F (x*y)+z (x*y)-z -(x*y)+z -(x*y)-z Rounded to the destination precision, with
bounded exponent; however, if the exact values
of x*y and z are equal in magnitude with signs
resulting in the FMA operation producing 0, the
rounding behavior described in Table 2-1.
If unmasked floating-point exceptions are signaled (invalid operation, denormal operand, overflow, underflow, or
inexact result) the result register is left unchanged and a floating-point exception handler is invoked.
2.3.1 FMA Instruction Operand Order and Arithmetic Behavior
FMA instruction mnemonics are defined explicitly with an ordered three digits, e.g. VFMADD132PD. The value of
each digit refers to the ordering of the three source operand as defined by instruction encoding specification:
• ‘1’: The first source operand (also the destination operand) in the syntactical order listed in this specification.
• ‘2’: The second source operand in the syntactical order. This is a YMM/XMM register, encoded using VEX prefix.
• ‘3’: The third source operand in the syntactical order. The first and third operand are encoded following ModR/M
encoding rules.
The ordering of each digit within the mnemonic refers to the floating-point data listed on the right-hand side of the
arithmetic equation of each FMA operation (see Table 2-2):
• The first position in the three digits of a FMA mnemonic refers to the operand position of the first FP data
expressed in the arithmetic equation of FMA operation, the multiplicand.
• The second position in the three digits of a FMA mnemonic refers to the operand position of the second FP data
expressed in the arithmetic equation of FMA operation, the multiplier.
• The third position in the three digits of a FMA mnemonic refers to the operand position of the FP data being
added/subtracted to the multiplication result.
Note the non-numerical result of an FMA operation does not resemble the mathematically-defined commutative
property between the multiplicand and the multiplier values (see Table 2-2). Consequently, software tools (such as
an assembler) may support a complementary set of FMA mnemonics for each FMA instruction for ease of programming
to take advantage of the mathematical property of commutative multiplications. For example, an assembler
may optionally support the complementary mnemonic “VFMADD312PD“ in addition to the true mnemonic
“VFMADD132PD“. The assembler will generate the same instruction opcode sequence corresponding to
VFMADD132PD. The processor executes VFMADD132PD and report any NAN conditions based on the definition of
VFMADD132PD. Similarly, if the complementary mnemonic VFMADD123PD is supported by an assembler at source
level, it must generate the opcode sequence corresponding to VFMADD213PD; the complementary mnemonic
VFMADD321PD must produce the opcode sequence defined by VFMADD231PD. In the absence of FMA operations
reporting a NAN result, the numerical results of using either mnemonic with an assembler supporting both
mnemonics will match the behavior defined in Table 2-2. Support for the complementary FMA mnemonics by software
tools is optional.
2.4 ACCESSING YMM REGISTERS
z
r=(x*y)
+z
r=(x*y)
-z
r =
-(x*y)+z
r=
-(x*y)-z
Comment
The lower 128 bits of a YMM register is aliased to the corresponding XMM register. Legacy SSE instructions (i.e.
SIMD instructions operating on XMM state but not using the VEX prefix, also referred to non-VEX encoded SIMD
instructions) will not access the upper bits (255:128) of the YMM registers. AVX and FMA instructions with a VEX
prefix and vector length of 128-bits zeroes the upper 128 bits of the YMM register. See Chapter 2, “Programming
Considerations with 128-bit SIMD Instructions” for more details.
2-8 Ref. # 319433-014