Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

This page was intentionally left blank. OPCODE MAP Ref. # 319433-014 A-7
OPCODE MAP Table A-2. One-byte Opcode Map: (00H — F7H) * 0 1 2 3 4 5 6 7 0 ADD PUSH ESi64 POP ESi64 Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz 1 ADC PUSH SS i64 Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz 2 AND SEG=ES Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz (Prefix) 3 XOR SEG=SS Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz (Prefix) 4 INC i64 general register / REX o64 Prefixes eAX REX eCX REX.B eDX REX.X eBX REX.XB A-8 Ref. # 319433-014 eSP REX.R eBP REX.RB eSI REX.RX POP SS i64 DAA i64 AAA i64 eDI REX.RXB 5 PUSHd64 general register rAX/r8 rCX/r9 rDX/r10 rBX/r11 rSP/r12 rBP/r13 rSI/r14 rDI/r15 6 PUSHAi64 / PUSHADi64 POPAi64 / POPADi64 BOUNDi64 Gv, Ma ARPLi64 Ew, Gw MOVSXDo64 Gv, Ev SEG=FS (Prefix) SEG=GS (Prefix) Operand Size (Prefix) Address Size (Prefix) 7 Jccf64 , Jb - Short-displacement jump on condition O NO B/NAE/C NB/AE/NC Z/E NZ/NE BE/NA NBE/A 8 Immediate Grp 11A TEST XCHG Eb, Ib Ev, Iz Eb, Ibi64 Ev, Ib Eb, Gb Ev, Gv Eb, Gb Ev, Gv 9 NOP PAUSE(F3) XCHG r8, rAX A MOV MOVS/B AL, Ob rAX, Ov Ob, AL Ov, rAX Yb, Xb XCHG word, double-word or quad-word register with rAX rCX/r9 rDX/r10 rBX/r11 rSP/r12 rBP/r13 rSI/r14 rDI/r15 MOVS/W/D/Q Yv, Xv CMPS/B Xb, Yb CMPS/W/D Xv, Yv B MOV immediate byte into byte register AL/R8L, Ib CL/R9L, Ib DL/R10L, Ib BL/R11L, Ib AH/R12L, Ib CH/R13L, Ib DH/R14L, Ib BH/R15L, Ib C Shift Grp 21A RETNf64 RETN Iw f64 LESi64 LDS Gz, Mp VEX+2byte i64 Grp 11 Gz, Mp VEX+1byte 1A - MOV Eb, Ib Ev, Ib Eb, Ib Ev, Iz D Shift Grp 21A AAMi64 AAD Ib i64 XLAT/ Eb, 1 Ev, 1 Eb, CL Ev, CL Ib XLATB E LOOPNE f64 / LOOPNZ f64 Jb F LOCK (Prefix) LOOPE f64 / LOOPZ f64 Jb LOOP f64 Jb REPNE XACQUIRE (Prefix) JrCXZ f64 / Jb REP/REPE XRELEASE (Prefix) IN OUT AL, Ib eAX, Ib Ib, AL Ib, eAX HLT CMC Unary Grp 3 1A Eb Ev
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE ELSE DEST
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PCMPEQQ (
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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Page 375 and 376: INSTRUCTION SET REFERENCE - VEX-ENC
Page 387 and 388: INTEL® TRANSACTIONAL SYNCHRONIZATI
Page 407 and 408: ADDITIONAL NEW INSTRUCTIONS -------
Page 409 and 410: ADDITIONAL NEW INSTRUCTIONS • If
Page 411 and 412: ADDITIONAL NEW INSTRUCTIONS ADCX
Page 413 and 414: ADDITIONAL NEW INSTRUCTIONS ADOX
Page 415 and 416: ADDITIONAL NEW INSTRUCTIONS Compati
Page 417 and 418: ADDITIONAL NEW INSTRUCTIONS Flags A
Page 419 and 420: ADDITIONAL NEW INSTRUCTIONS STAC—
Page 421 and 422: OPCODE MAP D The reg field of the M
Page 423 and 424: OPCODE MAP • A ModR/M byte is req
Page 425: OPCODE MAP A.2.5 Superscripts Utili
Page 429 and 430: OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
Page 431 and 432: OPCODE MAP 8 9 A B C D E F Table A-
Page 433 and 434: OPCODE MAP 0 Table A-4. Three-byte
Page 435 and 436: OPCODE MAP 0 66 1 66 2 66 3 4 66 5
Page 437 and 438: OPCODE MAP A.4 OPCODE EXTENSIONS FO
Page 439 and 440: OPCODE MAP Opcode Group Mod 7,6 pfx
Page 441 and 442: OPCODE MAP Table A-8 shows the map
Page 447 and 448: OPCODE MAP Table A-20 shows the opc
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Page 451 and 452: INSTRUCTION SUMMARY VEX.256 Encodin
Page 457 and 458: INSTRUCTION SUMMARY Note 3: It is e
Page 459 and 460: INSTRUCTION SUMMARY Table B-2. Prom
Page 461 and 462: INSTRUCTION SUMMARY Table B-3. VEX-
Page 463 and 464: INSTRUCTION SUMMARY Opcode Instruct
Page 473 and 474: SSE extensions flag . . . . . . . .
Page 475 and 476: SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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