Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

Intel C/C++ Compiler Intrinsic Equivalent (V)PSLLDQ: __m128i _mm_slli_si128 ( __m128i a, const int imm) VPSLLDQ: __m256i _mm256_slli_si256 ( __m256i a, const int imm) SIMD Floating-Point Exceptions None Other Exceptions See Exceptions Type 4 INSTRUCTION SET REFERENCE Ref. # 319433-014 5-133
INSTRUCTION SET REFERENCE PSLLW/PSLLD/PSLLQ — Bit Shift Left Opcode/ <strong>Instruction</strong> Op/ En 64/32 -bit Mode CPUID Feature Flag Description 66 0F F1/r B V/V SSE2 Shift words in xmm1 left by amount specified in xmm2/m128 while shifting in 0s. PSLLW xmm1, xmm2/m128 66 0F 71 /6 ib A V/V SSE2 Shift words in xmm1 left by imm8 while shifting in 0s. PSLLW xmm1, imm8 66 0F F2 /r B V/V SSE2 Shift doublewords in xmm1 left by amount specified in xmm2/m128 while shifting in 0s. PSLLD xmm1, xmm2/m128 66 0F 72 /6 ib A V/V SSE2 Shift doublewords in xmm1 left by imm8 while shifting in 0s. PSLLD xmm1, imm8 66 0F F3 /r B V/V SSE2 Shift quadwords in xmm1 left by amount specified in xmm2/m128 while shifting in 0s. PSLLQ xmm1, xmm2/m128 66 0F 73 /6 ib A V/V SSE2 Shift quadwords in xmm1 left by imm8 while shifting in 0s. PSLLQ xmm1, imm8 VEX.NDS.128.66.0F.WIG F1 /r D V/V AVX Shift words in xmm2 left by amount specified in xmm3/m128 while shifting in 0s. VPSLLW xmm1, xmm2, xmm3/m128 VEX.NDD.128.66.0F.WIG 71 /6 ib C V/V AVX Shift words in xmm2 left by imm8 while shifting in 0s. VPSLLW xmm1, xmm2, imm8 VEX.NDS.128.66.0F.WIG F2 /r D V/V AVX Shift doublewords in xmm2 left by amount specified in xmm3/m128 while shifting in 0s. VPSLLD xmm1, xmm2, xmm3/m128 VEX.NDD.128.66.0F.WIG 72 /6 ib C V/V AVX Shift doublewords in xmm2 left by imm8 while shifting in 0s. VPSLLD xmm1, xmm2, imm8 VEX.NDS.128.66.0F.WIG F3 /r D V/V AVX Shift quadwords in xmm2 left by amount specified in xmm3/m128 while shifting in 0s. VPSLLQ xmm1, xmm2, xmm3/m128 VEX.NDD.128.66.0F.WIG 73 /6 ib C V/V AVX Shift quadwords in xmm2 left by imm8 while shifting in 0s. VPSLLQ xmm1, xmm2, imm8 VEX.NDS.256.66.0F.WIG F1 /r D V/V AVX2 Shift words in ymm2 left by amount specified in xmm3/m128 while shifting in 0s. VPSLLW ymm1, ymm2, xmm3/m128 VEX.NDD.256.66.0F.WIG 71 /6 ib C V/V AVX2 Shift words in ymm2 left by imm8 while shifting in 0s. VPSLLW ymm1, ymm2, imm8 VEX.NDS.256.66.0F.WIG F2 /r D V/V AVX2 Shift doublewords in ymm2 left by amount specified in xmm3/m128 while shifting in 0s. VPSLLD ymm1, ymm2, xmm3/m128 5-134 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE ELSE DEST
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PCMPEQQ (
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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Page 171 and 172: INSTRUCTION SET REFERENCE VPMINUD (
Page 173 and 174: INSTRUCTION SET REFERENCE PMOVMSKB
Page 175 and 176: INSTRUCTION SET REFERENCE Opcode/ I
Page 177 and 178: INSTRUCTION SET REFERENCE VPMOVSXWQ
Page 179 and 180: INSTRUCTION SET REFERENCE PMOVZX
Page 181 and 182: INSTRUCTION SET REFERENCE Packed_Ze
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Page 185 and 186: INSTRUCTION SET REFERENCE Operation
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Page 189 and 190: INSTRUCTION SET REFERENCE PMULHUW
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Page 195 and 196: INSTRUCTION SET REFERENCE PMULLW/PM
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Page 199 and 200: INSTRUCTION SET REFERENCE PMULUDQ
Page 201 and 202: INSTRUCTION SET REFERENCE POR — B
Page 203 and 204: INSTRUCTION SET REFERENCE PSADBW
Page 205 and 206: INSTRUCTION SET REFERENCE PSHUFB
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Page 229 and 230: INSTRUCTION SET REFERENCE PSRLDQ
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Page 241 and 242: INSTRUCTION SET REFERENCE PSUBSB/PS
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Page 245 and 246: INSTRUCTION SET REFERENCE PUNPCKHBW
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Page 249 and 250: INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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