Intel® Architecture Instruction Set Extensions Programming Reference

SYSTEM PROGRAMMING MODEL
The processor supplied init values for each processor state component used by XRSTOR is listed in Table 3-7.
The action of XSAVE is listed in Table 3-8.
Table 3-6. XRSTOR Action on MXCSR, XMM Registers, YMM Registers
EDX:EAX
Bit 2 Bit 1
XSATE_BV
Bit 2 Bit 1
MXCSR YMM_H Registers XMM Registers
0 0 X X None None None
0 1 X 0 Load/Check None Init by processor
0 1 X 1 Load/Check None Load
1 0 0 X Load/Check Init by processor None
1 0 1 X Load/Check Load None
1 1 0 0 Load/Check Init by processor Init by processor
1 1 0 1 Load/Check Init by processor Load
1 1 1 0 Load/Check Load Init by processor
1 1 1 1 Load/Check Load Load
Table 3-7. Processor Supplied Init Values XRSTOR May Use
Processor State Component Processor Supplied Register Values
FCW ← 037FH; FTW ← 0FFFFH; FSW ← 0H; FPU CS ← 0H;
x87 FPU State
FPU DS ← 0H; FPU IP ← 0H; FPU DP ← 0; ST0-ST7 ← 0;
SSE State 1
If 64-bit Mode: XMM0-XMM15 ← 0H;
Else XMM0-XMM7 ← 0H
YMM State
NOTES:
1. MXCSR state is not updated by processor supplied values. MXCSR state can only be updated by XRSTOR from state information
stored in XSAVE/XRSTOR area.
1
If 64-bit Mode: YMM0_H-YMM15_H ← 0H;
Else YMM0_H-YMM7_H ← 0H
Table 3-8. XSAVE Action on MXCSR, XMM, YMM Register
EDX:EAX
XFEATURE_ENABLED_MAS
K MXCSR YMM_H Registers XMM Registers
Bit 2 Bit 1 Bit 2 Bit 1
0 0 X X None None None
0 1 X 1 Store None Store
0 1 X 0 None None None
1 0 0 X None None None
1 0 1 1 Store Store None
1 1 0 0 None None None
1 1 0 1 Store None Store
1 1 1 1 Store Store Store
3-4 Ref. # 319433-014