Intel® Architecture Instruction Set Extensions Programming Reference

Description
Instruction Operand Encoding
INSTRUCTION SET REFERENCE
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA
Unpacks and interleaves the high-order data elements (bytes, words, doublewords, and quadwords) of the first
source operand and second source operand into the destination operand. (Figure F-2 shows the unpack operation
for bytes in 64-bit operands.). The low-order data elements are ignored.
Figure 5-5. 256-bit VPUNPCKHDQ Instruction Operation
When the source data comes from a 128-bit memory operand an implementation may fetch only the appropriate
64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.
The PUNPCKHBW instruction interleaves the high-order bytes of the source and destination operands, the
PUNPCKHWD instruction interleaves the high-order words of the source and destination operands, the
PUNPCKHDQ instruction interleaves the high order doubleword (or doublewords) of the source and destination
operands, and the PUNPCKHQDQ instruction interleaves the high-order quadwords of the source and destination
operands.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (255:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (127:128) of the corresponding YMM register are
zeroed.
VEX.256 encoded version: The second source operand is an YMM register or a 256-bit memory location. The first
source operand and destination operands are YMM registers.
Operation
SRC
255
Y7 Y6 Y5
Y4
INTERLEAVE_HIGH_BYTES_256b (SRC1, SRC2)
DEST[7:0] SRC1[71:64]
DEST[15:8] SRC2[71:64]
DEST[23:16] SRC1[79:72]
DEST[31:24] SRC2[79:72]
DEST[39:32] SRC1[87:80]
DEST[47:40] SRC2[87:80]
DEST[55:48] SRC1[95:88]
DEST[63:56] SRC2[95:88]
DEST[71:64] SRC1[103:96]
DEST[79:72] SRC2[103:96]
DEST[87:80] SRC1[111:104]
Y3 Y2 Y1 Y0 X7 X6 X5 X4
DEST
31
255
0
255 31
Y7 X7 Y6 X6 Y3 X3 Y2
X3 X2 X1
Ref. # 319433-014 5-161
X2
0
X0
0