Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

IF (imm8[7] == 1) THEN DEST[127:112] SRC2[127:112] ELSE DEST[127:112] SRC1[127:112] IF (imm8[0] == 1) THEN DEST[143:128] SRC2[143:128] ELSE DEST[143:128] SRC1[143:128] IF (imm8[1] == 1) THEN DEST[159:144] SRC2[159:144] ELSE DEST[159:144] SRC1[159:144] IF (imm8[2] == 1) THEN DEST[175:160] SRC2[175:160] ELSE DEST[175:160] SRC1[175:160] IF (imm8[3] == 1) THEN DEST[191:176] SRC2[191:176] ELSE DEST[191:176] SRC1[191:176] IF (imm8[4] == 1) THEN DEST[207:192] SRC2[207:192] ELSE DEST[207:192] SRC1[207:192] IF (imm8[5] == 1) THEN DEST[223:208] SRC2[223:208] ELSE DEST[223:208] SRC1[223:208] IF (imm8[6] == 1) THEN DEST[239:224] SRC2[239:224] ELSE DEST[239:224] SRC1[239:224] IF (imm8[7] == 1) THEN DEST[255:240] SRC2[255:240] ELSE DEST[255:240] SRC1[255:240] VPBLENDW (VEX.128 encoded version) IF (imm8[0] == 1) THEN DEST[15:0] SRC2[15:0] ELSE DEST[15:0] SRC1[15:0] IF (imm8[1] == 1) THEN DEST[31:16] SRC2[31:16] ELSE DEST[31:16] SRC1[31:16] IF (imm8[2] == 1) THEN DEST[47:32] SRC2[47:32] ELSE DEST[47:32] SRC1[47:32] IF (imm8[3] == 1) THEN DEST[63:48] SRC2[63:48] ELSE DEST[63:48] SRC1[63:48] IF (imm8[4] == 1) THEN DEST[79:64] SRC2[79:64] ELSE DEST[79:64] SRC1[79:64] IF (imm8[5] == 1) THEN DEST[95:80] SRC2[95:80] ELSE DEST[95:80] SRC1[95:80] IF (imm8[6] == 1) THEN DEST[111:96] SRC2[111:96] ELSE DEST[111:96] SRC1[111:96] IF (imm8[7] == 1) THEN DEST[127:112] SRC2[127:112] ELSE DEST[127:112] SRC1[127:112] DEST[VLMAX:128] 0 PBLENDW (128-bit Legacy SSE version) IF (imm8[0] == 1) THEN DEST[15:0] SRC[15:0] ELSE DEST[15:0] DEST[15:0] IF (imm8[1] == 1) THEN DEST[31:16] SRC[31:16] ELSE DEST[31:16] DEST[31:16] IF (imm8[2] == 1) THEN DEST[47:32] SRC[47:32] ELSE DEST[47:32] DEST[47:32] IF (imm8[3] == 1) THEN DEST[63:48] SRC[63:48] ELSE DEST[63:48] DEST[63:48] IF (imm8[4] == 1) THEN DEST[79:64] SRC[79:64] ELSE DEST[79:64] DEST[79:64] IF (imm8[5] == 1) THEN DEST[95:80] SRC[95:80] ELSE DEST[95:80] DEST[95:80] IF (imm8[6] == 1) THEN DEST[111:96] SRC[111:96] ELSE DEST[111:96] DEST[111:96] IF (imm8[7] == 1) THEN DEST[127:112] SRC[127:112] INSTRUCTION SET REFERENCE Ref. # 319433-014 5-47
INSTRUCTION SET REFERENCE ELSE DEST[127:112] DEST[127:112] DEST[VLMAX:128] (Unmodified) Intel C/C++ Compiler Intrinsic Equivalent (V)PBLENDW: __m128i _mm_blend_epi16 (__m128i v1, __m128i v2, const int mask) VPBLENDW: __m256i _mm256_blend_epi16 (__m256i v1, __m256i v2, const int mask) SIMD Floating-Point Exceptions None Other Exceptions See Exceptions Type 4 5-48 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
Page 81 and 82: INSTRUCTION FORMAT The VEX.vvvv fie
Page 83 and 84: INSTRUCTION FORMAT 4.1.8 The Third
Page 85 and 86: INSTRUCTION FORMAT NOTES: 1. If Mod
Page 87 and 88: INSTRUCTION SET REFERENCE (V)ADDSD
Page 89 and 90: INSTRUCTION SET REFERENCE register
Page 91 and 92: INSTRUCTION SET REFERENCE MPSADBW
Page 93 and 94: INSTRUCTION SET REFERENCE SRC2_BYTE
Page 95 and 96: INSTRUCTION SET REFERENCE VMPSADBW
Page 97 and 98: INSTRUCTION SET REFERENCE DEST[79:6
Page 99 and 100: INSTRUCTION SET REFERENCE Operation
Page 101 and 102: INSTRUCTION SET REFERENCE PACKSSWB/
Page 105 and 106: INSTRUCTION SET REFERENCE PACKUSDW
Page 107 and 108: INSTRUCTION SET REFERENCE TMP[239:2
Page 109 and 110: INSTRUCTION SET REFERENCE DEST[119:
Page 111 and 112: INSTRUCTION SET REFERENCE PADDB/PAD
Page 113 and 114: INSTRUCTION SET REFERENCE PADDQ (Le
Page 115 and 116: INSTRUCTION SET REFERENCE PADDSB/PA
Page 117 and 118: INSTRUCTION SET REFERENCE PADDUSB/P
Page 119 and 120: INSTRUCTION SET REFERENCE PALIGNR
Page 121 and 122: INSTRUCTION SET REFERENCE PAND —
Page 123 and 124: INSTRUCTION SET REFERENCE PANDN —
Page 125 and 126: INSTRUCTION SET REFERENCE PAVGB/PAV
Page 127 and 128: INSTRUCTION SET REFERENCE PBLENDVB
Page 129 and 130: INSTRUCTION SET REFERENCE IF (MASK[
Page 131: INSTRUCTION SET REFERENCE PBLENDW
Page 135 and 136: INSTRUCTION SET REFERENCE Descripti
Page 137 and 138: INSTRUCTION SET REFERENCE PCMPEQQ (
Page 139 and 140: INSTRUCTION SET REFERENCE Descripti
Page 141 and 142: INSTRUCTION SET REFERENCE Intel C/C
Page 145 and 146: INSTRUCTION SET REFERENCE PHADDSW
Page 147 and 148: INSTRUCTION SET REFERENCE PHSUBW/PH
Page 153 and 154: INSTRUCTION SET REFERENCE PMADDUBSW
Page 155 and 156: INSTRUCTION SET REFERENCE VPMADDWD
Page 157 and 158: INSTRUCTION SET REFERENCE VEX.128 e
Page 171 and 172: INSTRUCTION SET REFERENCE VPMINUD (
Page 173 and 174: INSTRUCTION SET REFERENCE PMOVMSKB
Page 175 and 176: INSTRUCTION SET REFERENCE Opcode/ I
Page 177 and 178: INSTRUCTION SET REFERENCE VPMOVSXWQ
Page 179 and 180: INSTRUCTION SET REFERENCE PMOVZX
Page 181 and 182: INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE DEST[15:0
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE DEST[175:
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE DEST[95:8
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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