Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

ELSE DEST[63:0] 0; FI; IF SRC1[127:64] > SRC2[127:64] THEN DEST[127:64] FFFFFFFFFFFFFFFFH; ELSE DEST[127:64] 0; FI; VPCMPGTB (VEX.256 encoded version) DEST[127:0] COMPARE_BYTES_GREATER(SRC1[127:0],SRC2[127:0]) DEST[255:128] COMPARE_BYTES_GREATER(SRC1[255:128],SRC2[255:128]) VPCMPGTB (VEX.128 encoded version) DEST[127:0] COMPARE_BYTES_GREATER(SRC1[127:0],SRC2[127:0]) DEST[VLMAX:128] 0 PCMPGTB (128-bit Legacy SSE version) DEST[127:0] COMPARE_BYTES_GREATER(DEST[127:0],SRC[127:0]) DEST[VLMAX:128] (Unmodified) VPCMPGTW (VEX.256 encoded version) DEST[127:0] COMPARE_WORDS_GREATER(SRC1[127:0],SRC2[127:0]) DEST[255:128] COMPARE_WORDS_GREATER(SRC1[255:128],SRC2[255:128]) VPCMPGTW (VEX.128 encoded version) DEST[127:0] COMPARE_WORDS_GREATER(SRC1[127:0],SRC2[127:0]) DEST[VLMAX:128] 0 PCMPGTW (128-bit Legacy SSE version) DEST[127:0] COMPARE_WORDS_GREATER(DEST[127:0],SRC[127:0]) DEST[VLMAX:128] (Unmodified) VPCMPGTD (VEX.256 encoded version) DEST[127:0] COMPARE_DWORDS_GREATER(SRC1[127:0],SRC2[127:0]) DEST[255:128] COMPARE_DWORDS_GREATER(SRC1[255:128],SRC2[255:128]) VPCMPGTD (VEX.128 encoded version) DEST[127:0] COMPARE_DWORDS_GREATER(SRC1[127:0],SRC2[127:0]) DEST[VLMAX:128] 0 PCMPGTD (128-bit Legacy SSE version) DEST[127:0] COMPARE_DWORDS_GREATER(DEST[127:0],SRC[127:0]) DEST[VLMAX:128] (Unmodified) VPCMPGTQ (VEX.256 encoded version) DEST[127:0] COMPARE_QWORDS_GREATER(SRC1[127:0],SRC2[127:0]) DEST[255:128] COMPARE_QWORDS_GREATER(SRC1[255:128],SRC2[255:128]) VPCMPGTQ (VEX.128 encoded version) DEST[127:0] COMPARE_QWORDS_GREATER(SRC1[127:0],SRC2[127:0]) DEST[VLMAX:128] 0 PCMPGTQ (128-bit Legacy SSE version) DEST[127:0] COMPARE_QWORDS_GREATER(DEST[127:0],SRC2[127:0]) DEST[VLMAX:128] (Unmodified) INSTRUCTION SET REFERENCE Ref. # 319433-014 5-55
INSTRUCTION SET REFERENCE Intel C/C++ Compiler Intrinsic Equivalent (V)PCMPGTB: __m128i _mm_cmpgt_epi8 ( __m128i a, __m128i b) (V)PCMPGTW: __m128i _mm_cmpgt_epi16 ( __m128i a, __m128i b) (V)PCMPGTD: __m128i _mm_cmpgt_epi32 ( __m128i a, __m128i b) (V)PCMPGTQ: __m128i _mm_cmpgt_epi64(__m128i a, __m128i b); VPCMPGTB: __m256i _mm256_cmpgt_epi8 ( __m256i a, __m256i b) VPCMPGTW: __m256i _mm256_cmpgt_epi16 ( __m256i a, __m256i b) VPCMPGTD: __m256i _mm256_cmpgt_epi32 ( __m256i a, __m256i b) VPCMPGTQ: __m256i _mm256_cmpgt_epi64( __m256i a, __m256i b); SIMD Floating-Point Exceptions None Other Exceptions See Exceptions Type 4 5-56 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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Page 111 and 112: INSTRUCTION SET REFERENCE PADDB/PAD
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Page 117 and 118: INSTRUCTION SET REFERENCE PADDUSB/P
Page 119 and 120: INSTRUCTION SET REFERENCE PALIGNR
Page 121 and 122: INSTRUCTION SET REFERENCE PAND —
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Page 125 and 126: INSTRUCTION SET REFERENCE PAVGB/PAV
Page 127 and 128: INSTRUCTION SET REFERENCE PBLENDVB
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Page 131 and 132: INSTRUCTION SET REFERENCE PBLENDW
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Page 137 and 138: INSTRUCTION SET REFERENCE PCMPEQQ (
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Page 145 and 146: INSTRUCTION SET REFERENCE PHADDSW
Page 147 and 148: INSTRUCTION SET REFERENCE PHSUBW/PH
Page 153 and 154: INSTRUCTION SET REFERENCE PMADDUBSW
Page 155 and 156: INSTRUCTION SET REFERENCE VPMADDWD
Page 157 and 158: INSTRUCTION SET REFERENCE VEX.128 e
Page 171 and 172: INSTRUCTION SET REFERENCE VPMINUD (
Page 173 and 174: INSTRUCTION SET REFERENCE PMOVMSKB
Page 175 and 176: INSTRUCTION SET REFERENCE Opcode/ I
Page 177 and 178: INSTRUCTION SET REFERENCE VPMOVSXWQ
Page 179 and 180: INSTRUCTION SET REFERENCE PMOVZX
Page 181 and 182: INSTRUCTION SET REFERENCE Packed_Ze
Page 183 and 184: INSTRUCTION SET REFERENCE Other Exc
Page 187 and 188: INSTRUCTION SET REFERENCE temp13[31
Page 189 and 190: INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE DEST[15:0
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE DEST[175:
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE DEST[95:8
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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