Intel® Architecture Instruction Set Extensions Programming Reference

INVPCID — Invalidate Processor Context ID
Opcode/Instruction Op/
En
Description
64/32
-bit
Mode
CPUID
Feature
Flag
Instruction Operand Encoding
INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS
Description
66 0F 38 82 /r A NE/V INVPCID Invalidates entries in the TLBs and paging-structure caches based on
invalidation type in r32 and descriptor in m128.
INVPCID r32, m128
66 0F 38 82 /r A V/NE INVPCID Invalidates entries in the TLBs and paging-structure caches based on
invalidation type in r64 and descriptor in m128.
INVPCID r64, m128
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r) ModRM:r/m (r) NA NA
Invalidates mappings in the translation lookaside buffers (TLBs) and paging-structure caches based on the invalidation
type specified in the first operand and processor context identifier (PCID) invalidate descriptor specified in
the second operand. The INVPCID descriptor is specified as a 16-byte memory operand and has no alignment
restriction.
The layout of the INVPCID descriptor is shown in Figure 7-3. In 64-bit mode the linear address field (bits 127:64)
in the INVPCID descriptor must satisfy canonical requirement unless the linear address field is ignored.
127 64 63 12 11 0
Linear Address Reserved (must be zero) PCID
Figure 7-3. INVPCID Descriptor
Outside IA-32e mode, the register operand is always 32 bits, regardless of the value of CS.D. In 64-bit mode the
register operand has 64 bits; however, if bits 63:32 of the register operand are not zero, INVPCID fails due to an
attempt to use an unsupported INVPCID type (see below).
The INVPCID types supported by a logical processors are:
• Individual-address invalidation: If the INVPCID type is 0, the logical processor invalidates mappings for a single
linear address and tagged with the PCID specified in the INVPCID descriptor, except global translations. The
instruction may also invalidate global translations, mappings for other linear addresses, or mappings tagged
with other PCIDs.
• Single-context invalidation: If the INVPCID type is 1, the logical processor invalidates all mappings tagged with
the PCID specified in the INVPCID descriptor except global translations. In some cases, it may invalidate
mappings for other PCIDs as well.
• All-context invalidation: If the INVPCID type is 2, the logical processor invalidates all mappings tagged with any
PCID.
• All-context invalidation, retaining global translations: If the INVPCID type is 3, the logical processor invalidates
all mappings tagged with any PCID except global translations, ignoring the INVPCID descriptor. The instruction
may also invalidate global translations as well.
If an unsupported INVPCID type is specified, or if the reserved field in the descriptor is not zero, the instruction
fails.
Ref. # 319433-014 7-23