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Intel® Architecture Instruction Set Extensions Programming Reference

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INTEL® ADVANCED VECTOR EXTENSIONS<br />

• Support for 256-bit wide vectors and SIMD register set. 256-bit register state is managed by Operating System<br />

using XSAVE/XRSTOR instructions introduced in 45 nm Intel 64 processors (see IA-32 <strong>Intel®</strong> <strong>Architecture</strong><br />

Software Developer’s Manual, Volumes 2B and 3A).<br />

• <strong>Instruction</strong> syntax support for generalized three-operand syntax to improve instruction programming flexibility<br />

and efficient encoding of new instruction extensions.<br />

• Enhancement of legacy 128-bit SIMD instruction extensions to support three-operand syntax and to simplify<br />

compiler vectorization of high-level language expressions.<br />

• <strong>Instruction</strong> encoding format using a new prefix (referred to as VEX) to provide compact, efficient encoding for<br />

three-operand syntax, vector lengths, compaction of SIMD prefixes and REX functionality.<br />

• FMA extensions and enhanced floating-point compare instructions add support for IEEE-754-2008 standard.<br />

1.3.1 256-Bit Wide SIMD Register Support<br />

Intel AVX introduces support for 256-bit wide SIMD registers (YMM0-YMM7 in operating modes that are 32-bit or<br />

less, YMM0-YMM15 in 64-bit mode). The lower 128-bits of the YMM registers are aliased to the respective 128-bit<br />

XMM registers.<br />

255<br />

1.3.2 <strong>Instruction</strong> Syntax Enhancements<br />

Intel AVX employs an instruction encoding scheme using a new prefix (known as a “VEX” prefix). <strong>Instruction</strong><br />

encoding using the VEX prefix can directly encode a register operand within the VEX prefix. This supports two new<br />

instruction syntax in Intel 64 architecture:<br />

• A non-destructive operand (in a three-operand instruction syntax): The non-destructive source reduces the<br />

number of registers, register-register copies and explicit load operations required in typical SSE loops, reduces<br />

code size, and improves micro-fusion opportunities.<br />

• A third source operand (in a four-operand instruction syntax) via the upper 4 bits in an 8-bit immediate field.<br />

Support for the third source operand is defined for selected instructions (e.g., VBLENDVPD, VBLENDVPS, and<br />

PBLENDVB).<br />

Two-operand instruction syntax previously expressed as<br />

ADDPS xmm1, xmm2/m128<br />

now can be expressed in three-operand syntax as<br />

VADDPS xmm1, xmm2, xmm3/m128<br />

128<br />

YMM0<br />

YMM1<br />

. . .<br />

YMM15<br />

XMM0<br />

XMM1<br />

XMM15<br />

1-2 Ref. # 319433-014<br />

127<br />

Bit#<br />

0

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