Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
PADDSB/PADDSW — Add Packed Signed Integers with Signed Saturation
Opcode/
Instruction
Description
Op/
En
64/32
-bit
Mode
CPUID
Feature
Flag
Description
66 0F EC /r A V/V SSE2 Add packed signed byte integers from xmm2/m128 and xmm1 and
saturate the results.
PADDSB xmm1, xmm2/m128
66 0F ED /r A V/V SSE2 Add packed signed word integers from xmm2/m128 and xmm1 and
saturate the results.
PADDSW xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG EC /r B V/V AVX Add packed signed byte integers from xmm2, and xmm3/m128 and
store the saturated results in xmm1.
VPADDSB xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F.WIG ED /r B V/V AVX Add packed signed word integers from xmm2, and xmm3/m128 and
store the saturated results in xmm1.
VPADDSW xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F.WIG EC /r B V/V AVX2 Add packed signed byte integers from ymm2, and ymm3/m256 and
store the saturated results in ymm1.
VPADDSB ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F.WIG ED /r B V/V AVX2 Add packed signed word integers from ymm2, and ymm3/m256 and
store the saturated results in ymm1.
VPADDSW ymm1, ymm2,
ymm3/m256
Instruction Operand Encoding
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA
(V)PADDSB performs a SIMD add of the packed signed integers with saturation from the first source operand and
second source operand and stores the packed integer results in the destination operand. When an individual byte
result is beyond the range of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value
of 7FH or 80H, respectively, is written to the destination operand.
(V)PADDSW performs a SIMD add of the packed signed word integers with saturation from the first source operand
and second source operand and stores the packed integer results in the destination operand. When an individual
word result is beyond the range of a signed word integer (that is, greater than 7FFFH or less than 8000H), the saturated
value of 7FFFH or 8000H, respectively, is written to the destination operand.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (255:128) of the
corresponding YMM register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or a 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (255:128) of the corresponding YMM register destination are unmodified.
5-30 Ref. # 319433-014