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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exception SIMD Floating-Point Exception, #XF Real Virtual 8086 Protected Cause of Exception X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions Precision exception (PE) X X X A result could not be represented exactly in the destination format. 78 CVTSI2SS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology CVTSS2SD Convert Scalar Single-Precision Floating-Point to Scalar Double-Precision Floating-Point Converts a single-precision floating-point value in the low-order 32 bits of an XMM register or a 32-bit memory location to a double-precision floating-point value and writes the converted value in the low-order 64 bits of another XMM register. The highorder 64 bits in the destination XMM register are not modified. Mnemonic Opcode Description CVTSS2SD xmm1, xmm2/mem32 F3 0F 5A /r Converts scalar single-precision floating-point value in an XMM register or 32-bit memory location to double-precision floating-point value in the destination XMM register. xmm1 xmm2/mem32 127 64 63 0 127 32 31 0 convert cvtss2sd.eps Related Instructions CVTPD2PS, CVTPS2PD, CVTSD2SS rFLAGS Affected None MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. CVTSS2SD 79
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