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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 278 PSHUFD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology PSHUFHW Packed Shuffle High Words Moves any one of the four packed words in the high-order quadword of an XMM register or 128-bit memory location to each word in the high-order quadword of another XMM register. In each case, the value of the destination word is determined by a two-bit field in the immediate-byte operand, with bits 0 and 1 selecting the contents of the low-order word, bits 2 and 3 selecting the second word, bits 4 and 5 selecting the third word, and bits 6 and 7 selecting the high-order word. Refer to Table 1-5 on page 280. A word in the source operand may be copied to more than one word in the destination. The low-order quadword of the source operand is copied to the low-order quadword of the destination register. Mnemonic Opcode Description PSHUFHW xmm1, xmm2/mem128, imm8 F3 0F 70 /r ib Shuffles packed 16-bit values in high-order quadword of an XMM register or 128-bit memory location and puts the result in highorder quadword of another XMM register. xmm1 xmm2/mem128 127 112 111 96 95 80 79 64 63 0 127 112 111 96 95 80 79 64 63 0 imm8 7 0 mux mux mux mux pshufhw.eps PSHUFHW 279
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