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AMD 64-Bit Technology - ECE User Home Pages

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26568—Rev. 3.02—August 2002<br />

<strong>AMD</strong> <strong>64</strong>-<strong>Bit</strong> <strong>Technology</strong><br />

Exceptions<br />

Exception<br />

Invalid opcode, #UD<br />

Real<br />

X<br />

Virtual<br />

8086 Protected Cause of Exception<br />

X<br />

X<br />

The SSE instructions are not supported, as indicated by bit 25<br />

of CPUID standard function 1.<br />

X<br />

X<br />

X<br />

The emulate bit (EM) of CR0 was set to 1.<br />

X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR)<br />

of CR4 was cleared to 0.<br />

Device not available, X X X The task-switch bit (TS) of CR0 was set to 1.<br />

#NM<br />

Stack, #SS X X X A memory address exceeded the stack segment limit or was<br />

non-canonical.<br />

General protection, #GP<br />

X<br />

X<br />

X<br />

A memory address exceeded a data segment limit or was<br />

non-canonical.<br />

X<br />

X<br />

A null data segment was used to reference memory.<br />

The destination operand was in a non-writable segment.<br />

X X X The memory operand was not aligned on a 16-byte<br />

boundary.<br />

Page fault, #PF X X A page fault resulted from the execution of the instruction.<br />

MOVAPS 143

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