25.02.2015 Views

AMD 64-Bit Technology - ECE User Home Pages

AMD 64-Bit Technology - ECE User Home Pages

AMD 64-Bit Technology - ECE User Home Pages

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

<strong>AMD</strong> <strong>64</strong>-<strong>Bit</strong> <strong>Technology</strong> 26568—Rev. 3.02—August 2002<br />

PUNPCKHQDQ<br />

Unpack and Interleave High Quadwords<br />

Unpacks the high-order quadwords from the first and second source operands and<br />

packs them into interleaved quadwords in the destination (first source). The first<br />

source/destination is an XMM register, and the second source operand is another<br />

XMM register or 128-bit memory location. The low-order quadwords of the source<br />

operands are ignored.<br />

If the second source operand is all 0s, the destination contains the quadword from the<br />

first source operand zero-extended to 128 bits. This operation is useful for expanding<br />

unsigned <strong>64</strong>-bit values to unsigned 128-bit operands for subsequent processing that<br />

requires higher precision.<br />

Mnemonic Opcode Description<br />

PUNPCKHQDQ xmm1, xmm2/mem128 66 0F 6D /r Unpacks high-order quadwords in an XMM register<br />

and another XMM register or 128-bit memory location<br />

and packs them into interleaved quadwords in the<br />

destination XMM register.<br />

xmm1<br />

xmm2/mem128<br />

127 <strong>64</strong> 63 0<br />

127 <strong>64</strong> 63 0<br />

copy<br />

copy<br />

127<br />

<strong>64</strong> 63 0<br />

punpckhqdq.eps<br />

Related Instructions<br />

PUNPCKHBW, PUNPCKHDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ,<br />

PUNPCKLQDQ, PUNPCKLWD<br />

328 PUNPCKHQDQ

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!