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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 CVTDQ2PD Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Converts two packed 32-bit signed integer values in the low-order 64 bits of an XMM register or a 64-bit memory location to two packed double-precision floating-point values and writes the converted values in another XMM register. Mnemonic Opcode Description CVTDQ2PD xmm1, xmm2/mem64 F3 0F E6 /r Converts packed doubleword signed integers in an XMM register or 64-bit memory location to double-precision floating-point values in the destination XMM register. xmm1 xmm2/mem64 127 64 63 0 127 64 63 32 31 0 convert convert cvtdq2pd.eps Related Instructions CVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI, CVTTSD2SI rFLAGS Affected None MXCSR Flags Affected None 42 CVTDQ2PD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. CVTDQ2PD 43
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