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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 PMAXSW Packed Maximum Signed Words Compares each of the packed 16-bit signed integer values in the first source operand with the corresponding packed 16-bit signed integer value in the second source operand and writes the numerically greater of the two values for each comparison in the corresponding word of the destination (first source). The first source/destination and second source operands are an XMM register and an XMM register or 128-bit memory location. Mnemonic Opcode Description PMAXSW xmm1, xmm2/mem128 66 0F EE /r Compares packed signed 16-bit integer values in an XMM register and another XMM register or 128-bit memory location and writes the greater value of each comparison in destination XMM register. xmm1 . . . . . . 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 . . . . . . xmm2/mem128 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 . . . . . . maximum maximum pmaxsw-128.eps Related Instructions PMAXUB, PMINSW, PMINUB rFLAGS Affected None MXCSR Flags Affected None 254 PMAXSW
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 in CPUID standard function 1; and the AMD extensions to MMX are not supported, as indicated by bit 22 of CPUID extended function 8000_0001. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X A memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. PMAXSW 255
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