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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Table 1-8. Immediate-Byte Operand Encoding for SHUFPS Destination Bits Filled Immediate-Byte Bit Field Value of Bit Field Source 1 Bits Moved Source 2 Bits Moved 0 31–0 — 31–0 1–0 1 63–32 — 2 95–64 — 3 127–96 — 0 31–0 — 63–32 3–2 1 63–32 — 2 95–64 — 3 127–96 — 0 — 31–0 95–64 5–4 1 — 63–32 2 — 95–64 3 — 127–96 0 — 31–0 127–96 7–6 1 — 63–32 2 — 95–64 3 — 127–96 Related Instructions SHUFPS rFLAGS Affected None MXCSR Flags Affected None 354 SHUFPS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. SHUFPS 355
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