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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 CVTPD2PS Convert Packed Double-Precision Floating-Point to Packed Single-Precision Floating-Point Converts two packed double-precision floating-point values in an XMM register or a 128-bit memory location to two packed single-precision floating-point values and writes the converted values in the low-order 64 bits of another XMM register. The high-order 64 bits in the destination XMM register are cleared to all 0s. Mnemonic Opcode Description CVTPD2PS xmm1, xmm2/mem128 66 0F 5A /r Converts packed double-precision floating-point values in an XMM register or 128-bit memory location to packed single-precision floating-point values in the destination XMM register. xmm1 xmm2/mem128 127 64 63 32 31 0 0 127 64 63 0 convert convert cvtpd2ps.eps If the result of the conversion is an inexact value, the value is rounded as specified by the rounding control bits (RC) in the MXCSR register. Related Instructions CVTPS2PD, CVTSD2SS, CVTSS2SD rFLAGS Affected None 52 CVTPD2PS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE Exceptions M M M M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. SIMD Floating-Point Exception, #XF X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions Invalid-operation X X X A source operand was an SNaN value. exception (IE) Overflow exception (OE) X X X A rounded result was too large to fit into the format of the destination operand. CVTPD2PS 53
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