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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 PMULHUW Packed Multiply High Unsigned Word Multiplies each packed unsigned 16-bit values in the first source operand by the corresponding packed unsigned word in the second source operand and writes the high-order 16 bits of each intermediate 32-bit result in the corresponding word of the destination (first source). The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PMULHUW xmm1, xmm2/mem128 66 0F E4 /r Multiplies packed 16-bit values in an XMM register by the packed 16-bit values in another XMM register or 128-bit memory location and writes the high-order 16 bits of each result in the destination XMM register. xmm1 . . . . . . 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 xmm2/mem128 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 . . . . . . . . . . . . multiply multiply pmulhuw-128.eps Related Instructions PMADDWD, PMULHW, PMULLW, PMULUDQ rFLAGS Affected None MXCSR Flags Affected None 264 PMULHUW
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 in CPUID standard function 1; and the AMD extensions to MMX are not supported, as indicated by bit 22 of CPUID extended function 8000_0001. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. PMULHUW 265
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