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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 16 ANDNPD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology ANDNPS Logical Bitwise AND NOT Packed Single-Precision Floating-Point Performs a bitwise logical AND of the four packed single-precision floating-point values in the second source operand and the one’s-complement of the corresponding four packed single-precision floating-point values in the first source operand and writes the result in the destination (first source). The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description ANDNPS xmm1, xmm2/mem128 0F 55 /r Performs bitwise logical AND NOT of four packed single-precision floating-point values in an XMM register and in another XMM register or 128-bit memory location and writes the result in the destination XMM register. xmm1 xmm2/mem128 127 96 95 64 63 32 31 0 127 96 95 64 63 32 31 0 invert AND invert AND invert AND invert AND andnps.eps Related Instructions ANDNPD, ANDPD, ANDPS, ORPD, ORPS, XORPD, XORPS rFLAGS Affected None ANDNPS 17
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